📄 clock.tan.rpt
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Timing Analyzer report for clock
Thu Mar 20 11:02:46 2008
Version 5.1 Build 176 10/26/2005 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clk'
6. tco
7. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+----------------------------------+-----------------------+-----------------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+-----------------------+-----------------------+------------+----------+--------------+
; Worst-case tco ; N/A ; None ; 31.911 ns ; counter24:u5|count[5] ; hourl[3] ; clk ; -- ; 0 ;
; Clock Setup: 'clk' ; N/A ; None ; 275.03 MHz ( period = 3.636 ns ) ; counter24:u5|count[0] ; counter24:u5|count[3] ; clk ; clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+----------------------------------+-----------------------+-----------------------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1C6Q240C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-------+------------------------------------------------+-----------------------+-----------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+-----------------------+-----------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 275.03 MHz ( period = 3.636 ns ) ; counter24:u5|count[0] ; counter24:u5|count[3] ; clk ; clk ; None ; None ; 3.375 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter24:u5|count[2] ; counter24:u5|count[3] ; clk ; clk ; None ; None ; 3.222 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter24:u5|count[0] ; counter24:u5|count[1] ; clk ; clk ; None ; None ; 2.942 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter24:u5|count[0] ; counter24:u5|count[2] ; clk ; clk ; None ; None ; 2.938 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter24:u5|count[0] ; counter24:u5|count[5] ; clk ; clk ; None ; None ; 2.926 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter24:u5|count[1] ; counter24:u5|count[3] ; clk ; clk ; None ; None ; 2.873 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter24:u5|count[1] ; counter24:u5|count[5] ; clk ; clk ; None ; None ; 2.853 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter24:u5|count[1] ; counter24:u5|count[4] ; clk ; clk ; None ; None ; 2.851 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter24:u5|count[2] ; counter24:u5|count[1] ; clk ; clk ; None ; None ; 2.789 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter24:u5|count[2] ; counter24:u5|count[2] ; clk ; clk ; None ; None ; 2.785 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter24:u5|count[2] ; counter24:u5|count[5] ; clk ; clk ; None ; None ; 2.773 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter24:u5|count[0] ; counter24:u5|count[4] ; clk ; clk ; None ; None ; 2.611 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter24:u5|count[1] ; counter24:u5|count[1] ; clk ; clk ; None ; None ; 2.440 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter24:u5|count[1] ; counter24:u5|count[2] ; clk ; clk ; None ; None ; 2.436 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter24:u5|count[5] ; counter24:u5|count[3] ; clk ; clk ; None ; None ; 2.342 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter24:u5|count[4] ; counter24:u5|count[3] ; clk ; clk ; None ; None ; 2.182 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter24:u5|count[5] ; counter24:u5|count[5] ; clk ; clk ; None ; None ; 2.165 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter24:u5|count[3] ; counter24:u5|count[3] ; clk ; clk ; None ; None ; 2.062 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter24:u5|count[3] ; counter24:u5|count[5] ; clk ; clk ; None ; None ; 2.049 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter24:u5|count[3] ; counter24:u5|count[4] ; clk ; clk ; None ; None ; 2.047 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter24:u5|count[4] ; counter24:u5|count[5] ; clk ; clk ; None ; None ; 2.005 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter10:u3|count[0] ; counter10:u3|count[2] ; clk ; clk ; None ; None ; 1.947 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter10:u3|count[0] ; counter10:u3|count[1] ; clk ; clk ; None ; None ; 1.945 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter10:u3|count[0] ; counter10:u3|count[3] ; clk ; clk ; None ; None ; 1.944 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter10:u1|count[0] ; counter10:u1|count[3] ; clk ; clk ; None ; None ; 1.918 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter10:u1|count[0] ; counter10:u1|count[2] ; clk ; clk ; None ; None ; 1.917 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter24:u5|count[5] ; counter24:u5|count[1] ; clk ; clk ; None ; None ; 1.909 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter24:u5|count[5] ; counter24:u5|count[2] ; clk ; clk ; None ; None ; 1.905 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter24:u5|count[2] ; counter24:u5|count[4] ; clk ; clk ; None ; None ; 1.867 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter24:u5|count[4] ; counter24:u5|count[1] ; clk ; clk ; None ; None ; 1.749 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter24:u5|count[4] ; counter24:u5|count[2] ; clk ; clk ; None ; None ; 1.745 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter10:u1|count[3] ; counter10:u1|count[1] ; clk ; clk ; None ; None ; 1.655 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter10:u1|count[3] ; counter10:u1|c ; clk ; clk ; None ; None ; 1.645 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter24:u5|count[3] ; counter24:u5|count[1] ; clk ; clk ; None ; None ; 1.629 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter10:u3|count[2] ; counter10:u3|c ; clk ; clk ; None ; None ; 1.628 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter24:u5|count[3] ; counter24:u5|count[2] ; clk ; clk ; None ; None ; 1.625 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter6:u2|count[0] ; counter6:u2|count[2] ; clk ; clk ; None ; None ; 1.535 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter6:u2|count[0] ; counter6:u2|count[1] ; clk ; clk ; None ; None ; 1.535 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter6:u4|count[1] ; counter6:u4|count[2] ; clk ; clk ; None ; None ; 1.379 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter6:u4|count[1] ; counter6:u4|count[1] ; clk ; clk ; None ; None ; 1.369 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter6:u4|count[0] ; counter6:u4|count[2] ; clk ; clk ; None ; None ; 1.300 ns ;
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