clock.map.rpt

这是一个实现时分秒的时钟功能的源码

+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 74    ;
;     -- Combinational with no register       ; 50    ;
;     -- Register only                        ; 7     ;
;     -- Combinational with a register        ; 17    ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 33    ;
;     -- 3 input functions                    ; 23    ;
;     -- 2 input functions                    ; 6     ;
;     -- 1 input functions                    ; 5     ;
;     -- 0 input functions                    ; 0     ;
;         -- Combinational cells for routing  ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 74    ;
;     -- arithmetic mode                      ; 0     ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 0     ;
;     -- asynchronous clear/load mode         ; 24    ;
;                                             ;       ;
; Total registers                             ; 24    ;
; I/O pins                                    ; 64    ;
; Maximum fan-out node                        ; reset ;
; Maximum fan-out                             ; 24    ;
; Total fan-out                               ; 334   ;
; Average fan-out                             ; 2.42  ;
+---------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                    ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |clock                     ; 74 (4)      ; 24           ; 0           ; 64   ; 0            ; 50 (4)       ; 7 (0)             ; 17 (0)           ; 0 (0)           ; 0 (0)      ; |clock              ;
;    |counter10:u1|          ; 7 (7)       ; 5            ; 0           ; 0    ; 0            ; 2 (2)        ; 2 (2)             ; 3 (3)            ; 0 (0)           ; 0 (0)      ; |clock|counter10:u1 ;
;    |counter10:u3|          ; 7 (7)       ; 5            ; 0           ; 0    ; 0            ; 2 (2)        ; 2 (2)             ; 3 (3)            ; 0 (0)           ; 0 (0)      ; |clock|counter10:u3 ;
;    |counter24:u5|          ; 11 (11)     ; 6            ; 0           ; 0    ; 0            ; 5 (5)        ; 3 (3)             ; 3 (3)            ; 0 (0)           ; 0 (0)      ; |clock|counter24:u5 ;
;    |counter6:u2|           ; 4 (4)       ; 4            ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (4)            ; 0 (0)           ; 0 (0)      ; |clock|counter6:u2  ;
;    |counter6:u4|           ; 4 (4)       ; 4            ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (4)            ; 0 (0)           ; 0 (0)      ; |clock|counter6:u4  ;
;    |decoder:u10|           ; 7 (7)       ; 0            ; 0           ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |clock|decoder:u10  ;
;    |decoder:u11|           ; 2 (2)       ; 0            ; 0           ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |clock|decoder:u11  ;
;    |decoder:u6|            ; 7 (7)       ; 0            ; 0           ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |clock|decoder:u6   ;
;    |decoder:u7|            ; 7 (7)       ; 0            ; 0           ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |clock|decoder:u7   ;
;    |decoder:u8|            ; 7 (7)       ; 0            ; 0           ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |clock|decoder:u8   ;
;    |decoder:u9|            ; 7 (7)       ; 0            ; 0           ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |clock|decoder:u9   ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 24    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 4     ;
; Number of registers using Asynchronous Load  ; 20    ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                             ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output   ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------+
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |clock|counter24:u5|count[3] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in F:/mywork/clock/clock.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Thu Mar 20 11:02:17 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clock -c clock
Info: Found 2 design units, including 1 entities, in source file counter10.vhd
    Info: Found design unit 1: counter10-Behavioral
    Info: Found entity 1: counter10
Info: Found 2 design units, including 1 entities, in source file counter6.vhd
    Info: Found design unit 1: counter6-Behavioral
    Info: Found entity 1: counter6
Info: Found 2 design units, including 1 entities, in source file counter24.vhd
    Info: Found design unit 1: counter24-Behavioral
    Info: Found entity 1: counter24
Info: Found 2 design units, including 1 entities, in source file decoder.vhd
    Info: Found design unit 1: decoder-Behavioral
    Info: Found entity 1: decoder
Info: Found 2 design units, including 1 entities, in source file clock.vhd
    Info: Found design unit 1: clock-Behavioral
    Info: Found entity 1: clock
Warning: Can't analyze file -- file F:/mywork/clock/clock.bdf is missing
Info: Elaborating entity "clock" for the top level hierarchy
Info: Elaborating entity "counter10" for hierarchy "counter10:u1"
Info: Elaborating entity "counter6" for hierarchy "counter6:u2"
Info: Elaborating entity "counter24" for hierarchy "counter24:u5"
Info: Elaborating entity "decoder" for hierarchy "decoder:u6"
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "hourl[5]" stuck at GND
Info: Implemented 138 device resources after synthesis - the final resource count might be different
    Info: Implemented 22 input pins
    Info: Implemented 42 output pins
    Info: Implemented 74 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings
    Info: Processing ended: Thu Mar 20 11:02:21 2008
    Info: Elapsed time: 00:00:05