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来自「使用verilog和VHDL两种硬件描述语言实现了一个ATA硬盘控制器」· 代码 · 共 11 行

/atahost_controller.v/1.2/Sun May 19 06:05:28 2002//
/atahost_pio_actrl.v/1.1/Mon Feb 18 14:26:46 2002//
/atahost_pio_tctrl.v/1.1/Mon Feb 18 14:26:46 2002//
/atahost_top.v/1.1/Mon Feb 18 14:26:46 2002//
/atahost_wb_slave.v/1.1/Mon Feb 18 14:26:46 2002//
/revision_history.txt/1.2/Sun May 19 06:05:28 2002//
/ro_cnt.v/1.1/Mon Feb 18 14:26:46 2002//
/timescale.v/1.1/Mon Feb 18 14:26:46 2002//
/ud_cnt.v/1.1/Mon Feb 18 14:26:46 2002//
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