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📄 dzxs.vht

📁 vhdl语言实现的16乘16的点阵显示设计代码
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	t_sig_o1_expected(2) <= '0';
	WAIT FOR 20000 ps;
	t_sig_o1_expected(2) <= '1';
	WAIT FOR 20000 ps;
	t_sig_o1_expected(2) <= '0';
	WAIT FOR 80000 ps;
	t_sig_o1_expected(2) <= '1';
	WAIT FOR 40000 ps;
	t_sig_o1_expected(2) <= '0';
	WAIT FOR 60000 ps;
	FOR i IN 1 TO 6249
	LOOP
		t_sig_o1_expected(2) <= '1';
		WAIT FOR 20000 ps;
		t_sig_o1_expected(2) <= '0';
		WAIT FOR 20000 ps;
		t_sig_o1_expected(2) <= '1';
		WAIT FOR 20000 ps;
		t_sig_o1_expected(2) <= '0';
		WAIT FOR 40000 ps;
		t_sig_o1_expected(2) <= '1';
		WAIT FOR 20000 ps;
		t_sig_o1_expected(2) <= '0';
		WAIT FOR 100000 ps;
		t_sig_o1_expected(2) <= '1';
		WAIT FOR 60000 ps;
		t_sig_o1_expected(2) <= '0';
		WAIT FOR 40000 ps;
	END LOOP;
	t_sig_o1_expected(2) <= '1';
	WAIT FOR 20000 ps;
	t_sig_o1_expected(2) <= '0';
	WAIT FOR 20000 ps;
	t_sig_o1_expected(2) <= '1';
	WAIT FOR 20000 ps;
	t_sig_o1_expected(2) <= '0';
	WAIT FOR 40000 ps;
	t_sig_o1_expected(2) <= '1';
	WAIT FOR 20000 ps;
	t_sig_o1_expected(2) <= '0';
WAIT;
END PROCESS t_prcs_hang_2;
-- expected hang[1]
t_prcs_hang_1: PROCESS
BEGIN
	t_sig_o1_expected(1) <= '0';
	WAIT FOR 30000 ps;
	FOR i IN 1 TO 6248
	LOOP
		FOR i IN 1 TO 2
		LOOP
			t_sig_o1_expected(1) <= '1';
			WAIT FOR 60000 ps;
			t_sig_o1_expected(1) <= '0';
			WAIT FOR 40000 ps;
		END LOOP;
		t_sig_o1_expected(1) <= '1';
		WAIT FOR 20000 ps;
		t_sig_o1_expected(1) <= '0';
		WAIT FOR 100000 ps;
	END LOOP;
	FOR i IN 1 TO 2
	LOOP
		t_sig_o1_expected(1) <= '1';
		WAIT FOR 60000 ps;
		t_sig_o1_expected(1) <= '0';
		WAIT FOR 40000 ps;
	END LOOP;
	t_sig_o1_expected(1) <= '1';
	WAIT FOR 20000 ps;
	t_sig_o1_expected(1) <= '0';
	WAIT FOR 100000 ps;
	FOR i IN 1 TO 2
	LOOP
		t_sig_o1_expected(1) <= '1';
		WAIT FOR 60000 ps;
		t_sig_o1_expected(1) <= '0';
		WAIT FOR 40000 ps;
	END LOOP;
	t_sig_o1_expected(1) <= '1';
	WAIT FOR 20000 ps;
	t_sig_o1_expected(1) <= '0';
	WAIT FOR 120000 ps;
	FOR i IN 1 TO 6249
	LOOP
		t_sig_o1_expected(1) <= '1';
		WAIT FOR 80000 ps;
		t_sig_o1_expected(1) <= '0';
		WAIT FOR 20000 ps;
		t_sig_o1_expected(1) <= '1';
		WAIT FOR 40000 ps;
		t_sig_o1_expected(1) <= '0';
		WAIT FOR 180000 ps;
	END LOOP;
	t_sig_o1_expected(1) <= '1';
	WAIT FOR 80000 ps;
	t_sig_o1_expected(1) <= '0';
	WAIT FOR 20000 ps;
	t_sig_o1_expected(1) <= '1';
	WAIT FOR 40000 ps;
	t_sig_o1_expected(1) <= '0';
	WAIT FOR 220000 ps;
	FOR i IN 1 TO 6249
	LOOP
		t_sig_o1_expected(1) <= '1';
		WAIT FOR 60000 ps;
		t_sig_o1_expected(1) <= '0';
		WAIT FOR 20000 ps;
		t_sig_o1_expected(1) <= '1';
		WAIT FOR 40000 ps;
		t_sig_o1_expected(1) <= '0';
		WAIT FOR 20000 ps;
		t_sig_o1_expected(1) <= '1';
		WAIT FOR 20000 ps;
		t_sig_o1_expected(1) <= '0';
		WAIT FOR 160000 ps;
	END LOOP;
	t_sig_o1_expected(1) <= '1';
	WAIT FOR 60000 ps;
	t_sig_o1_expected(1) <= '0';
	WAIT FOR 20000 ps;
	t_sig_o1_expected(1) <= '1';
	WAIT FOR 40000 ps;
	t_sig_o1_expected(1) <= '0';
	WAIT FOR 20000 ps;
	t_sig_o1_expected(1) <= '1';
	WAIT FOR 20000 ps;
	t_sig_o1_expected(1) <= '0';
	WAIT FOR 180000 ps;
	FOR i IN 1 TO 6249
	LOOP
		t_sig_o1_expected(1) <= '1';
		WAIT FOR 60000 ps;
		t_sig_o1_expected(1) <= '0';
		WAIT FOR 40000 ps;
		t_sig_o1_expected(1) <= '1';
		WAIT FOR 20000 ps;
		t_sig_o1_expected(1) <= '0';
		WAIT FOR 20000 ps;
		t_sig_o1_expected(1) <= '1';
		WAIT FOR 20000 ps;
		t_sig_o1_expected(1) <= '0';
		WAIT FOR 80000 ps;
		t_sig_o1_expected(1) <= '1';
		WAIT FOR 40000 ps;
		t_sig_o1_expected(1) <= '0';
		WAIT FOR 40000 ps;
	END LOOP;
	t_sig_o1_expected(1) <= '1';
	WAIT FOR 60000 ps;
	t_sig_o1_expected(1) <= '0';
	WAIT FOR 40000 ps;
	t_sig_o1_expected(1) <= '1';
	WAIT FOR 20000 ps;
	t_sig_o1_expected(1) <= '0';
	WAIT FOR 20000 ps;
	t_sig_o1_expected(1) <= '1';
	WAIT FOR 20000 ps;
	t_sig_o1_expected(1) <= '0';
	WAIT FOR 80000 ps;
	t_sig_o1_expected(1) <= '1';
	WAIT FOR 40000 ps;
	t_sig_o1_expected(1) <= '0';
	WAIT FOR 60000 ps;
	t_sig_o1_expected(1) <= '1';
	WAIT FOR 60000 ps;
	t_sig_o1_expected(1) <= '0';
	WAIT FOR 40000 ps;
	FOR i IN 1 TO 6249
	LOOP
		t_sig_o1_expected(1) <= '1';
		WAIT FOR 20000 ps;
		t_sig_o1_expected(1) <= '0';
		WAIT FOR 100000 ps;
		FOR i IN 1 TO 2
		LOOP
			t_sig_o1_expected(1) <= '1';
			WAIT FOR 60000 ps;
			t_sig_o1_expected(1) <= '0';
			WAIT FOR 40000 ps;
		END LOOP;
	END LOOP;
	t_sig_o1_expected(1) <= '1';
	WAIT FOR 20000 ps;
	t_sig_o1_expected(1) <= '0';
WAIT;
END PROCESS t_prcs_hang_1;
-- expected hang[0]
t_prcs_hang_0: PROCESS
BEGIN
	t_sig_o1_expected(0) <= '0';
	WAIT FOR 30000 ps;
	FOR i IN 1 TO 6248
	LOOP
		t_sig_o1_expected(0) <= '1';
		WAIT FOR 60000 ps;
		FOR i IN 1 TO 2
		LOOP
			t_sig_o1_expected(0) <= '0';
			WAIT FOR 60000 ps;
			t_sig_o1_expected(0) <= '1';
			WAIT FOR 20000 ps;
		END LOOP;
		t_sig_o1_expected(0) <= '0';
		WAIT FOR 100000 ps;
	END LOOP;
	t_sig_o1_expected(0) <= '1';
	WAIT FOR 60000 ps;
	FOR i IN 1 TO 2
	LOOP
		t_sig_o1_expected(0) <= '0';
		WAIT FOR 60000 ps;
		t_sig_o1_expected(0) <= '1';
		WAIT FOR 20000 ps;
	END LOOP;
	t_sig_o1_expected(0) <= '0';
	WAIT FOR 100000 ps;
	t_sig_o1_expected(0) <= '1';
	WAIT FOR 60000 ps;
	FOR i IN 1 TO 2
	LOOP
		t_sig_o1_expected(0) <= '0';
		WAIT FOR 60000 ps;
		t_sig_o1_expected(0) <= '1';
		WAIT FOR 20000 ps;
	END LOOP;
	t_sig_o1_expected(0) <= '0';
	WAIT FOR 120000 ps;
	FOR i IN 1 TO 6249
	LOOP
		t_sig_o1_expected(0) <= '1';
		WAIT FOR 60000 ps;
		t_sig_o1_expected(0) <= '0';
		WAIT FOR 60000 ps;
		t_sig_o1_expected(0) <= '1';
		WAIT FOR 20000 ps;
		t_sig_o1_expected(0) <= '0';
		WAIT FOR 180000 ps;
	END LOOP;
	t_sig_o1_expected(0) <= '1';
	WAIT FOR 60000 ps;
	t_sig_o1_expected(0) <= '0';
	WAIT FOR 60000 ps;
	t_sig_o1_expected(0) <= '1';
	WAIT FOR 20000 ps;
	t_sig_o1_expected(0) <= '0';
	WAIT FOR 220000 ps;
	FOR i IN 1 TO 6249
	LOOP
		t_sig_o1_expected(0) <= '1';
		WAIT FOR 60000 ps;
		t_sig_o1_expected(0) <= '0';
		WAIT FOR 40000 ps;
		t_sig_o1_expected(0) <= '1';
		WAIT FOR 20000 ps;
		t_sig_o1_expected(0) <= '0';
		WAIT FOR 20000 ps;
		t_sig_o1_expected(0) <= '1';
		WAIT FOR 20000 ps;
		t_sig_o1_expected(0) <= '0';
		WAIT FOR 160000 ps;
	END LOOP;
	t_sig_o1_expected(0) <= '1';
	WAIT FOR 60000 ps;
	t_sig_o1_expected(0) <= '0';
	WAIT FOR 40000 ps;
	t_sig_o1_expected(0) <= '1';
	WAIT FOR 20000 ps;
	t_sig_o1_expected(0) <= '0';
	WAIT FOR 20000 ps;
	t_sig_o1_expected(0) <= '1';
	WAIT FOR 20000 ps;
	t_sig_o1_expected(0) <= '0';
	WAIT FOR 180000 ps;
	FOR i IN 1 TO 6249
	LOOP
		t_sig_o1_expected(0) <= '1';
		WAIT FOR 60000 ps;
		t_sig_o1_expected(0) <= '0';
		WAIT FOR 40000 ps;
		t_sig_o1_expected(0) <= '1';
		WAIT FOR 20000 ps;
		t_sig_o1_expected(0) <= '0';
		WAIT FOR 20000 ps;
		t_sig_o1_expected(0) <= '1';
		WAIT FOR 20000 ps;
		t_sig_o1_expected(0) <= '0';
		WAIT FOR 80000 ps;
		t_sig_o1_expected(0) <= '1';
		WAIT FOR 40000 ps;
		t_sig_o1_expected(0) <= '0';
		WAIT FOR 40000 ps;
	END LOOP;
	t_sig_o1_expected(0) <= '1';
	WAIT FOR 60000 ps;
	t_sig_o1_expected(0) <= '0';
	WAIT FOR 40000 ps;
	t_sig_o1_expected(0) <= '1';
	WAIT FOR 20000 ps;
	t_sig_o1_expected(0) <= '0';
	WAIT FOR 20000 ps;
	t_sig_o1_expected(0) <= '1';
	WAIT FOR 20000 ps;
	t_sig_o1_expected(0) <= '0';
	WAIT FOR 80000 ps;
	t_sig_o1_expected(0) <= '1';
	WAIT FOR 40000 ps;
	t_sig_o1_expected(0) <= '0';
	WAIT FOR 80000 ps;
	t_sig_o1_expected(0) <= '1';
	WAIT FOR 20000 ps;
	t_sig_o1_expected(0) <= '0';
	WAIT FOR 60000 ps;
	t_sig_o1_expected(0) <= '1';
	WAIT FOR 20000 ps;
	FOR i IN 1 TO 6249
	LOOP
		t_sig_o1_expected(0) <= '0';
		WAIT FOR 100000 ps;
		t_sig_o1_expected(0) <= '1';
		WAIT FOR 60000 ps;
		FOR i IN 1 TO 2
		LOOP
			t_sig_o1_expected(0) <= '0';
			WAIT FOR 60000 ps;
			t_sig_o1_expected(0) <= '1';
			WAIT FOR 20000 ps;
		END LOOP;
	END LOOP;
	t_sig_o1_expected(0) <= '0';
WAIT;
END PROCESS t_prcs_hang_0;
-- expected lei[3]
t_prcs_lei_3: PROCESS
BEGIN
	t_sig_o2_expected(3) <= '0';
	WAIT FOR 150000 ps;
	FOR i IN 1 TO 31249
	LOOP
		t_sig_o2_expected(3) <= '1';
		WAIT FOR 160000 ps;
		t_sig_o2_expected(3) <= '0';
		WAIT FOR 160000 ps;
	END LOOP;
	t_sig_o2_expected(3) <= '1';
	WAIT FOR 160000 ps;
	t_sig_o2_expected(3) <= '0';
WAIT;
END PROCESS t_prcs_lei_3;
-- expected lei[2]
t_prcs_lei_2: PROCESS
BEGIN
	t_sig_o2_expected(2) <= '0';
	WAIT FOR 70000 ps;
	FOR i IN 1 TO 62499
	LOOP
		t_sig_o2_expected(2) <= '1';
		WAIT FOR 80000 ps;
		t_sig_o2_expected(2) <= '0';
		WAIT FOR 80000 ps;
	END LOOP;
	t_sig_o2_expected(2) <= '1';
	WAIT FOR 80000 ps;
	t_sig_o2_expected(2) <= '0';
WAIT;
END PROCESS t_prcs_lei_2;
-- expected lei[1]
t_prcs_lei_1: PROCESS
BEGIN
	t_sig_o2_expected(1) <= '0';
	WAIT FOR 30000 ps;
	FOR i IN 1 TO 124999
	LOOP
		t_sig_o2_expected(1) <= '1';
		WAIT FOR 40000 ps;
		t_sig_o2_expected(1) <= '0';
		WAIT FOR 40000 ps;
	END LOOP;
	t_sig_o2_expected(1) <= '1';
	WAIT FOR 40000 ps;
	t_sig_o2_expected(1) <= '0';
WAIT;
END PROCESS t_prcs_lei_1;
-- expected lei[0]
t_prcs_lei_0: PROCESS
BEGIN
	t_sig_o2_expected(0) <= '0';
	WAIT FOR 10000 ps;
	FOR i IN 1 TO 249999
	LOOP
		t_sig_o2_expected(0) <= '1';
		WAIT FOR 20000 ps;
		t_sig_o2_expected(0) <= '0';
		WAIT FOR 20000 ps;
	END LOOP;
	t_sig_o2_expected(0) <= '1';
	WAIT FOR 20000 ps;
	t_sig_o2_expected(0) <= '0';
WAIT;
END PROCESS t_prcs_lei_0;

-- Set trigger on real/expected o/ pattern changes                        

t_prcs_trigger_e : PROCESS(t_sig_o1_expected,t_sig_o2_expected)
BEGIN
	trigger_e <= NOT trigger_e;
END PROCESS t_prcs_trigger_e;

t_prcs_trigger_r : PROCESS(o1,o2)
BEGIN
	trigger_r <= NOT trigger_r;
END PROCESS t_prcs_trigger_r;


t_prcs_selfcheck : PROCESS
VARIABLE i : INTEGER := 1;
VARIABLE txt : LINE;

VARIABLE last_o1_exp : o1_type := (OTHERS => 'U');
VARIABLE last_o2_exp : o2_type := (OTHERS => 'U');

VARIABLE on_first_change : trackvec := "11";
BEGIN

WAIT UNTIL (sampler'LAST_VALUE = '1'OR sampler'LAST_VALUE = '0')
	AND sampler'EVENT;
IF (debug_tbench = '1') THEN
	write(txt,string'("Scanning pattern "));
	write(txt,i);
	writeline(output,txt);
	write(txt,string'("| expected "));write(txt,o1_name);write(txt,string'(" = "));write(txt,t_sig_o1_expected_prev);
	write(txt,string'("| expected "));write(txt,o2_name);write(txt,string'(" = "));write(txt,t_sig_o2_expected_prev);
	writeline(output,txt);
	write(txt,string'("| real "));write(txt,o1_name);write(txt,string'(" = "));write(txt,t_sig_o1_prev);
	write(txt,string'("| real "));write(txt,o2_name);write(txt,string'(" = "));write(txt,t_sig_o2_prev);
	writeline(output,txt);
	i := i + 1;
END IF;
IF ( t_sig_o1_expected_prev /= "XXXXXXXXXXXXXXXX" ) AND (t_sig_o1_expected_prev /= "UUUUUUUUUUUUUUUU" ) AND (t_sig_o1_prev /= t_sig_o1_expected_prev) AND (
	(t_sig_o1_expected_prev /= last_o1_exp) OR
	(on_first_change(1) = '1')
		) THEN
	throw_error("hang",t_sig_o1_expected_prev,t_sig_o1_prev);
	num_mismatches(0) <= num_mismatches(0) + 1;
	on_first_change(1) := '0';
	last_o1_exp := t_sig_o1_expected_prev;
END IF;
IF ( t_sig_o2_expected_prev /= "XXXX" ) AND (t_sig_o2_expected_prev /= "UUUU" ) AND (t_sig_o2_prev /= t_sig_o2_expected_prev) AND (
	(t_sig_o2_expected_prev /= last_o2_exp) OR
	(on_first_change(2) = '1')
		) THEN
	throw_error("lei",t_sig_o2_expected_prev,t_sig_o2_prev);
	num_mismatches(1) <= num_mismatches(1) + 1;
	on_first_change(2) := '0';
	last_o2_exp := t_sig_o2_expected_prev;
END IF;
    trigger_i <= NOT trigger_i;
END PROCESS t_prcs_selfcheck;


t_prcs_trigger_res : PROCESS(trigger_e,trigger_i,trigger_r)
BEGIN
	trigger <= trigger_i XOR trigger_e XOR trigger_r;
END PROCESS t_prcs_trigger_res;

t_prcs_endsim : PROCESS
VARIABLE txt : LINE;
VARIABLE total_mismatches : INTEGER := 0;
BEGIN
WAIT FOR 10000000000 ps;
total_mismatches := num_mismatches(0) + num_mismatches(1);
IF (total_mismatches = 0) THEN                                              
        write(txt,string'("Simulation passed !"));                        
        writeline(output,txt);                                              
ELSE                                                                        
        write(txt,total_mismatches);                                        
        write(txt,string'(" mismatched vectors : Simulation failed !"));  
        writeline(output,txt);                                              
END IF;                                                                     
WAIT;
END PROCESS t_prcs_endsim;

END ovec_arch;

LIBRARY ieee;                                               
USE ieee.std_logic_1164.all;                                

LIBRARY STD;                                                            
USE STD.textio.ALL;                                                     

USE WORK.dzxs_vhd_tb_types.ALL;                                         

ENTITY dzxs_vhd_vec_tst IS
END dzxs_vhd_vec_tst;
ARCHITECTURE dzxs_arch OF dzxs_vhd_vec_tst IS
-- constants                                                 
-- signals                                                   
SIGNAL t_sig_clk : STD_LOGIC;
SIGNAL t_sig_hang : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL t_sig_lei : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL t_sig_sampler : sample_type;

COMPONENT dzxs
	PORT (
	clk : IN STD_LOGIC;
	hang : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
	lei : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
	);
END COMPONENT;
COMPONENT dzxs_vhd_check_tst
PORT (
	o1 : IN o1_type;
	o2 : IN o2_type;
	sampler : IN sample_type
);
END COMPONENT;
COMPONENT dzxs_vhd_sample_tst
PORT (
	s1 : IN i1_type;
	sampler : OUT sample_type
	);
END COMPONENT;
BEGIN
	tb : dzxs
	PORT MAP (
-- list connections between master ports and signals
	clk => t_sig_clk,
	hang => t_sig_hang,
	lei => t_sig_lei
	);

-- clk
t_prcs_clk: PROCESS
BEGIN
LOOP
	t_sig_clk <= '0';
	WAIT FOR 10000 ps;
	t_sig_clk <= '1';
	WAIT FOR 10000 ps;
	IF (NOW >= 10000000000 ps) THEN WAIT; END IF;
END LOOP;
END PROCESS t_prcs_clk;
tb_sample : dzxs_vhd_sample_tst
PORT MAP (
	s1 => t_sig_clk,
	sampler => t_sig_sampler
	);

tb_out : dzxs_vhd_check_tst
PORT MAP (
	o1 => t_sig_hang,
	o2 => t_sig_lei,
	sampler => t_sig_sampler
	);
END dzxs_arch;
1234

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