dzxs.vhd

vhdl语言实现的16乘16的点阵显示设计代码

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

entity dzxs is
port(clk:in std_logic;
     hang:out std_logic_vector(15 downto 0);
     lei:out std_logic_vector(3 downto 0));
end dzxs;

architecture dzxs_16 of dzxs is

component shikong
PORT
	(
		CLK : IN STD_LOGIC;
		Q : OUT STD_LOGIC_VECTOR(1 downto 0)
	);
	end component;

component weixuan
PORT
	(
		CLK : IN STD_LOGIC;
		Q : OUT STD_LOGIC_VECTOR(3 downto 0)
	);
	end component;

component xianshi
PORT
	(
		SHI : IN STD_LOGIC_VECTOR(1 downto 0);
		WEI : IN STD_LOGIC_VECTOR(3 downto 0);
		Q : OUT STD_LOGIC_VECTOR(15 downto 0)
	);
	end component;
	
signal m:std_logic_vector(1 downto 0);
signal n:std_logic_vector(3 downto 0);
signal a:std_logic_vector(15 downto 0);
begin

u1:shikong port map(clk=>clk,q=>m);
u2:weixuan port map(clk=>clk,q=>n);
u3:xianshi port map(shi=>m,wei=>n,q=>a);
hang<=a;
lei<=n;

end dzxs_16;