dzxs.map.qmsg

vhdl语言实现的16乘16的点阵显示设计代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Sep 21 10:48:57 2007 " "Info: Processing started: Fri Sep 21 10:48:57 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off dzxs -c dzxs --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dzxs -c dzxs --generate_functional_sim_netlist" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Block1.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file Block1.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Block1 " "Info: Found entity 1: Block1" {  } { { "Block1.bdf" "" { Schematic "F:/VHDL练习/16乘16的点阵显示设计/Block1.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SHIKONG.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file SHIKONG.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 SHIKONG-SHIKONG_architecture " "Info: Found design unit 1: SHIKONG-SHIKONG_architecture" {  } { { "SHIKONG.vhd" "" { Text "F:/VHDL练习/16乘16的点阵显示设计/SHIKONG.vhd" 43 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 SHIKONG " "Info: Found entity 1: SHIKONG" {  } { { "SHIKONG.vhd" "" { Text "F:/VHDL练习/16乘16的点阵显示设计/SHIKONG.vhd" 29 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "WEIXUAN.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file WEIXUAN.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 WEIXUAN-WEIXUAN_architecture " "Info: Found design unit 1: WEIXUAN-WEIXUAN_architecture" {  } { { "WEIXUAN.vhd" "" { Text "F:/VHDL练习/16乘16的点阵显示设计/WEIXUAN.vhd" 43 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 WEIXUAN " "Info: Found entity 1: WEIXUAN" {  } { { "WEIXUAN.vhd" "" { Text "F:/VHDL练习/16乘16的点阵显示设计/WEIXUAN.vhd" 29 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "XIANSHI.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file XIANSHI.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 XIANSHI-XIANSHI_architecture " "Info: Found design unit 1: XIANSHI-XIANSHI_architecture" {  } { { "XIANSHI.vhd" "" { Text "F:/VHDL练习/16乘16的点阵显示设计/XIANSHI.vhd" 44 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 XIANSHI " "Info: Found entity 1: XIANSHI" {  } { { "XIANSHI.vhd" "" { Text "F:/VHDL练习/16乘16的点阵显示设计/XIANSHI.vhd" 29 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dzxs.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file dzxs.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 dzxs-dzxs_16 " "Info: Found design unit 1: dzxs-dzxs_16" {  } { { "dzxs.vhd" "" { Text "F:/VHDL练习/16乘16的点阵显示设计/dzxs.vhd" 11 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 dzxs " "Info: Found entity 1: dzxs" {  } { { "dzxs.vhd" "" { Text "F:/VHDL练习/16乘16的点阵显示设计/dzxs.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "dzxs " "Info: Elaborating entity \"dzxs\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SHIKONG SHIKONG:u1 " "Info: Elaborating entity \"SHIKONG\" for hierarchy \"SHIKONG:u1\"" {  } { { "dzxs.vhd" "u1" { Text "F:/VHDL练习/16乘16的点阵显示设计/dzxs.vhd" 43 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "WEIXUAN WEIXUAN:u2 " "Info: Elaborating entity \"WEIXUAN\" for hierarchy \"WEIXUAN:u2\"" {  } { { "dzxs.vhd" "u2" { Text "F:/VHDL练习/16乘16的点阵显示设计/dzxs.vhd" 44 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "XIANSHI XIANSHI:u3 " "Info: Elaborating entity \"XIANSHI\" for hierarchy \"XIANSHI:u3\"" {  } { { "dzxs.vhd" "u3" { Text "F:/VHDL练习/16乘16的点阵显示设计/dzxs.vhd" 45 -1 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "XIANSHI.vhd(70) " "Info: VHDL Case Statement information at XIANSHI.vhd(70): OTHERS choice is never selected" {  } { { "XIANSHI.vhd" "" { Text "F:/VHDL练习/16乘16的点阵显示设计/XIANSHI.vhd" 70 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "XIANSHI.vhd(92) " "Info: VHDL Case Statement information at XIANSHI.vhd(92): OTHERS choice is never selected" {  } { { "XIANSHI.vhd" "" { Text "F:/VHDL练习/16乘16的点阵显示设计/XIANSHI.vhd" 92 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "XIANSHI.vhd(114) " "Info: VHDL Case Statement information at XIANSHI.vhd(114): OTHERS choice is never selected" {  } { { "XIANSHI.vhd" "" { Text "F:/VHDL练习/16乘16的点阵显示设计/XIANSHI.vhd" 114 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "XIANSHI.vhd(136) " "Info: VHDL Case Statement information at XIANSHI.vhd(136): OTHERS choice is never selected" {  } { { "XIANSHI.vhd" "" { Text "F:/VHDL练习/16乘16的点阵显示设计/XIANSHI.vhd" 136 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "XIANSHI.vhd(140) " "Info: VHDL Case Statement information at XIANSHI.vhd(140): OTHERS choice is never selected" {  } { { "XIANSHI.vhd" "" { Text "F:/VHDL练习/16乘16的点阵显示设计/XIANSHI.vhd" 140 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/quartus ii 5.0/libraries/megafunctions/lpm_mux.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/quartus ii 5.0/libraries/megafunctions/lpm_mux.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_mux " "Info: Found entity 1: lpm_mux" {  } { { "lpm_mux.tdf" "" { Text "e:/quartus ii 5.0/libraries/megafunctions/lpm_mux.tdf" 72 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_jcc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mux_jcc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_jcc " "Info: Found entity 1: mux_jcc" {  } { { "db/mux_jcc.tdf" "" { Text "F:/VHDL练习/16乘16的点阵显示设计/db/mux_jcc.tdf" 22 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_3ec.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mux_3ec.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_3ec " "Info: Found entity 1: mux_3ec" {  } { { "db/mux_3ec.tdf" "" { Text "F:/VHDL练习/16乘16的点阵显示设计/db/mux_3ec.tdf" 22 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_ecc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mux_ecc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_ecc " "Info: Found entity 1: mux_ecc" {  } { { "db/mux_ecc.tdf" "" { Text "F:/VHDL练习/16乘16的点阵显示设计/db/mux_ecc.tdf" 22 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/quartus ii 5.0/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/quartus ii 5.0/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "e:/quartus ii 5.0/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/quartus ii 5.0/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/quartus ii 5.0/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "e:/quartus ii 5.0/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/quartus ii 5.0/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/quartus ii 5.0/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "e:/quartus ii 5.0/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/quartus ii 5.0/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/quartus ii 5.0/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "e:/quartus ii 5.0/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Sep 21 10:49:00 2007 " "Info: Processing ended: Fri Sep 21 10:49:00 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}