arm10_bed.v

arm10_verilog.rar是基于arm10的verilog代码

/*****************************************************************************
$RCSfile: arm10_bed.v,v $
$Revision: 1.4 $
$Author: kohlere $
$Date: 1999/05/07 15:35:32 $
$State: Exp $
$Source: /home/lefurgy/tmp/ISC-repository/isc/hardware/ARM10/behavioral/arm10_bed.v,v $
*****************************************************************************/
module arm10_bed();

/*------------------------------------------------------------------------
	Interconnections
------------------------------------------------------------------------*/
reg GCLK;
reg nRESET;	//0 for Reset
reg BIGEND;	//1 for Big Endian
reg [1:0] CHSE, CHSD;	//Handshake for Coprocessor
reg [31:0] saved_ir;
wire [4:0] InM;
wire LATECANCEL;
wire PASS;	
/*------------------------------------------------------------------------
	Structural Blocks
------------------------------------------------------------------------*/
arm10 xarm10(.nRESET(nRESET), .GCLK(GCLK), .BIGEND(BIGEND),
	     .CHSD(CHSD), .CHSE(CHSE), .LATECANCEL(LATECANCEL),
	     .PASS(PASS), .InM(InM));

/*------------------------------------------------------------------------
	Behavioral Blocks
------------------------------------------------------------------------*/

//
// Initialize & Reset Sequence
//
initial
begin
  nRESET = 1'b0;
  BIGEND = 1'b0;	//Little Endian Mode
  GCLK = 1'b0;
  CHSD = 2'b10;		//Copressor Absent
  CHSE = 2'b10;		//Copressor Absent
	
  saved_ir = 32'h00000000;	
  // To create SignalScan data
  // in order for this not to cause an error, 'verilog_sst' must be run
  // instead of 'verilog'
  $recordvars;
  // Read the LC-2 program into the memory of the machine
  $readmemh("testarm.vhx", xarm10.mem);
  #10 nRESET = 1'b1;
end

always #50 GCLK = ~GCLK;

//Print out Machine State Info, Cycle-by-cycle

always @(negedge GCLK)
begin
	$display("TIME[%t]\n\tPC = [%h]\tInst : %h",
		$realtime, xarm10.PC, xarm10.ir);
	$display("\tR0 = %h\tR5 = %h\tR10 = %h", xarm10.r0, xarm10.r5,
						xarm10.r10);
	$display("\tR1 = %h\tR6 = %h\tR11 = %h", xarm10.r1, xarm10.r6,
                                                xarm10.r11);
        $display("\tR2 = %h\tR7 = %h\tR12 = %h", xarm10.r2, xarm10.r7,
                                                xarm10.r12);
        $display("\tR3 = %h\tR8 = %h\tR13 = %h", xarm10.r3, xarm10.r8,
                                                xarm10.r13);
        $display("\tR4 = %h\tR9 = %h\tR14 = %h", xarm10.r4, xarm10.r9,
                                                xarm10.r14);
	$display("\t[N,Z,C,V] = [%b, %b, %b, %b]", xarm10.N, xarm10.Z,
						   xarm10.C, xarm10.V);
end

// To protect from an infinite loop or error
initial
begin
  # 20000;
  $finish(2);
end

/*======================================================================*/
endmodule	// lc2_bed
/*======================================================================*/