arm10.v

arm10_verilog.rar是基于arm10的verilog代码

                        else
                // RSC Instruction -- 2nd Opearand a Register
                            alu;
                    end
	 
		    8'h0F:
		    begin
                        if (ir[7:4] == 4'h9)
                // SMLALS Instrcution
			    mull;
                        else if ((ir[11:4] & 8'h09) == 8'h09)
                // LDRH immediate offset, write-back, up, post indexed
                            ldrh;
                        else
                // RSCS Instruction -- 2nd Operand a Register
                            alu;
                    end   

		    8'h10:
		    begin
			if (ir[11:4] == 8'h0B)
		// STRH register offset, no write-back, down, pre indexed
			    strh;
			else if (ir[11:4] == 8'h09)
		// SWP Word
			    swap;
			else if ((ir[11:0] == 8'h00) & (ir[21:16] == 6'h0F))
		// MRS CPSR to Rd
			    mrs;
			else
		// TST Instruction -- 2nd Operand a Register
			    alu;
		    end

		    8'h11:
		    begin
                        if ((ir[11:4] & 8'hF9) == 8'h09)
                // LDRHSB register offset, no write-back, down, pre indexed
                            ldrh;
                        else
		// TSTS Instruction -- 2nd Operand a Register
			    alu;
		    end

		    8'h12:
		    begin
                        if (ir[11:4] == 8'h0B)
                // STRH register offset, write-back, down, pre indexed
                            strh;
			else if ((Rd == 4'hF) && (ir[18:17] == 2'b00))
		// MSR to CPSR from Rd
			    msr;
			else
		// TEQ Instruction -- 2nd Operand a Register
			    alu;
		    end

		    8'h13:
		    begin
                        if ((ir[11:4] & 8'hF9) == 8'h09)
                // LDRHSB register offset, write-back, down, pre indexed
                            ldrh;
                        else                
		// TEQS Instruction -- 2nd Operand is a Register
			    alu;
		    end


		    8'h14:
		    begin
                        if (ir[7:4] == 4'hB)
                // STRH immediate offset, no write-back, down, pre indexed
                            strh;
			else if (ir[11:4] == 8'h09)
		// SWP Byte
			    swap;
			else if ((ir[11:4] == 8'h00) && (ir[21:16] == 6'h0F))
		// MRS SPSR to Rd
			    mrs;
			else
		// CMP Instruction -- 2nd Operand a Register
			    alu;
		    end

		    8'h15:
		    begin
                        if ((ir[11:4] & 8'h09) == 8'h09)
                // LDRHSB immediate offset, no write-back, down, pre indexed
                            ldrh;
                        else
		// CMPS Instruction -- 2nd Operand a Register
			    alu;
		    end
		
		    8'h16:
		    begin
                        if (ir[7:4] == 4'hB)
                // STRH immediate offset, write-back, down, pre indexed
                            strh;
                        else if ((Rd == 4'hF) && (ir[18:17] == 2'b00))
                // MSR to SPSR from Rd
                            msr;
                        else
                // CMN Instruction -- 2nd Operand a Register
                            alu;
		    end

		    8'h17:
		    begin
                        if ((ir[11:4] & 8'h09) == 8'h09)
                // LDRHSB immediate offset, write-back, down, pre indexed
                            ldrh;
                        else
                // CMNS Instruction -- 2nd Operand a Register
                            alu;   
                    end

		    8'h18:
		    begin
                        if (ir[11:4] == 8'h0B)
                // STRH register offset, no write-back, up, pre indexed
                            strh;
                        else
                // ORR Instruction -- 2nd Operand a Register
                            alu;   
                    end

		    8'h19:
		    begin
                        if ((ir[11:4] & 8'hF9) == 8'h09)
                // LDRHSB register offset, no write-back, up, pre indexed
                            ldrh;
                        else
                // ORRS Instruction -- 2nd Operand a Register
                            alu;
                    end

		    8'h1A:
                    begin
                        if (ir[11:4] == 8'h0B)
                // STRH register offset, write-back, up, pre indexed
                            strh;
                        else
                // MOV Instruction -- 2nd Operand a Register
                            alu;
                    end

		    8'h1B:
		    begin
                        if ((ir[11:4] & 8'hF9) == 8'h09)
                // LDRHSB register offset, write-back, up, pre indexed
                            ldrh;
                        else
                // MOVS Instruction -- 2nd Operand a Register
                            alu;
                    end

		    8'h1C:
		    begin
                        if (ir[7:4] == 4'hB)
                // STRH immediate offset, no write-back, up, pre indexed
                            strh;
                        else
                // BIC Instruction -- 2nd Operand a Register
                            alu;
                    end  

		    8'h1D:
		    begin
                        if ((ir[11:4] & 8'h09) == 8'h09)
                // LDRHSB immediate offset, no write-back, up, pre indexed
                            ldrh;
                        else
                // BICS Instruction -- 2nd Operand a Register
                            alu;
                    end 

		    8'h1E:
		    begin
                        if (ir[7:4] == 4'hB)
                // STRH immediate offset, write-back, up, pre indexed 
                            strh;
                        else
                // MVN Instruction -- 2nd Operand a Register
                            alu;
                    end

		    8'h1F:
		    begin
                        if ((ir[11:4] & 8'h09) == 8'h09)
                // LDRHSB immediate offset, write-back, up, pre indexed
                            ldrh;
                        else
                // MVNS Instruction -- 2nd Operand a Register
                            alu;
                    end

		// AND Instruction -- 2nd Operand an Immediate
		    8'h20: alu;	
			
		// ANDS Instruction -- 2nd Operand an Immediate
		    8'h21: alu;

		// EOR Instruction -- 2nd Operand an Immediate
                    8'h22: alu;

                // EORS Instruction -- 2nd Operand an Immediate
                    8'h23: alu;

                // SUB Instruction -- 2nd Operand an Immediate
                    8'h24: alu;

                // SUBS Instruction -- 2nd Operand an Immediate
                    8'h25: alu;

                // RSB Instruction -- 2nd Operand an Immediate
                    8'h26: alu;

                // RSBS Instruction -- 2nd Operand an Immediate
                    8'h27: alu;

                // ADD Instruction -- 2nd Operand an Immediate
                    8'h28: alu;

                // ADDS Instruction -- 2nd Operand an Immediate
                    8'h29: alu;

                // ADC Instruction -- 2nd Operand an Immediate
                    8'h2A: alu;

                // ADCS Instruction -- 2nd Operand an Immediate
                    8'h2B: alu;

                // SBC Instruction -- 2nd Operand an Immediate
                    8'h2C: alu;

                // SBCS Instruction -- 2nd Operand an Immediate
                    8'h2D: alu;

                // RSC Instruction -- 2nd Operand an Immediate
                    8'h2E: alu;

                // RSCS Instruction -- 2nd Operand an Immediate
                    8'h2F: alu;

                // TST Instruction -- 2nd Operand an Immediate
                    8'h30: alu;

                // TSTS Instruction -- 2nd Operand an Immediate
                    8'h31: alu;

                    8'h32: 
		    begin
		// MSR Immediate Value to CPSR
			if ((Rd == 4'hF)&&(ir[18:17] == 2'b0))
			    msr;
		// TEQ Instruction -- 2nd Operand an Immediate
			else
			    alu;
		    end

                // TEQS Instruction -- 2nd Operand an Immediate
                    8'h33: alu;

                // CMP Instruction -- 2nd Operand an Immediate
                    8'h34: alu;

                // CMPS Instruction -- 2nd Operand an Immediate
                    8'h35: alu;

                    8'h36:
                    begin
                // MSR Immediate Value to SPSR
                        if ((Rd == 4'hF)&&(ir[18:17] == 2'b0))
                            msr;
                // CMN Instruction -- 2nd Operand an Immediate
                        else
                            alu;
                    end

                // CMNS Instruction -- 2nd Operand an Immediate
                    8'h37: alu;

                // ORR Instruction -- 2nd Operand an Immediate
                    8'h38: alu;

                // ORRS Instruction -- 2nd Operand an Immediate
                    8'h39: alu;

                // MOV Instruction -- 2nd Operand an Immediate
                    8'h3A: alu;

                // MOVS Instruction -- 2nd Operand an Immediate
                    8'h3B: alu;

                // BIC Instruction -- 2nd Operand an Immediate
                    8'h3C: alu;

                // BICS Instruction -- 2nd Operand an Immediate
                    8'h3D: alu;

                // MVN Instruction -- 2nd Operand an Immediate
                    8'h3E: alu;

                // MVNS Instruction -- 2nd Operand an Immediate
                    8'h3F: alu;

                // Store Word, immediate, no write back, post dec
                    8'h40: strw;

                // Load Word, immediate, no write back, post dec         
                    8'h41: ldrw;

                // Store Word, immediate, write back, post dec
                    8'h42: strw;
                    
                // Load Word, immediate, write back, post dec
                    8'h43: ldrw;

                // Store Byte, immediate, no write back, post dec
                    8'h44: strw;
                
                // Load Byte, immediate, no write back, post dec
                    8'h45: ldrw;

                // Store Byte, immediate, write back, post dec
                    8'h46: strw;
                
                // Load Byte, immediate, write back, post dec
                    8'h47: ldrw;

                // Store Word, immediate, no write back, post inc
                    8'h48: strw;
                
                // Load Word, immediate, no write back, post inc
                    8'h49: ldrw;

                // Store Word, immediate, write back, post inc
                    8'h4A: strw;
                
                // Load Word, immediate, write back, post inc
                    8'h4B: ldrw;

                // Store Byte, immediate, no write back, post inc
                    8'h4C: strw;
                    
                // Load Byte, immediate, no write back, post inc
                    8'h4D: ldrw;

                // Store Byte, immediate, write back, post inc
                    8'h4E: strw;
                
                // Load Byte, immediate, write back, post inc
                    8'h4F: ldrw;
                
                // Store Word, immediate, no write back, pre dec
                    8'h50: strw;
                
                // Load Word, immediate, no write back, pre dec
                    8'h51: ldrw;

                // Store Word, immediate, write back, pre dec 
                    8'h52: strw;
                
                // Load Word, immediate, write back, pre dec 
                    8'h53: ldrw;

                // Store Byte, immediate, no write back, pre dec
                    8'h54: strw;
                
                // Load Byte, immediate, no write back, pre dec
                    8'h55: ldrw;
                
                // Store Byte, immediate, write back, pre dec 
                    8'h56: strw;
                    
                // Load Byte, immediate, write back, pre dec
                    8'h57: ldrw;

                // Store Word, immediate, no write back, pre inc
                    8'h58: strw;
                
                // Load Word, immediate, no write back, pre inc
                    8'h59: ldrw;

                // Store Word, immediate, write back, pre inc
                    8'h5A: strw;
                    
                // Load Word, immediate, write back, pre inc
                    8'h5B: ldrw;

                // Store Byte, immediate, no write back, pre inc
                    8'h5C: strw;
                
                // Load Byte, immediate, no write back, pre inc
                    8'h5D: ldrw;

                // Store Byte, immediate, write back, pre inc
                    8'h5E: strw;
                
                // Load Byte, immediate, write back, pre inc
                    8'h5F: ldrw;

		    8'h60: begin
		// Undefined Instruction
		    if (ir[4] == 1'b1)
			undefined;
		    else
		// Store Word, register, no write back, post dec
			strw;
		    end

		    8'h61: begin
                // Undefined Instruction
                    if (ir[4] == 1'b1)
                        undefined;
                    else
                // Load Word, register, no write back, post dec
                        ldrw;
                    end

		    8'h62: begin
                // Undefined Instruction
                    if (ir[4] == 1'b1)
                        undefined;
                    else
                // Store Word, register, write back, post dec
                        strw;