arm10.v

arm10_verilog.rar是基于arm10的verilog代码

/*****************************************************************************
$RCSfile: arm10.v,v $
$Revision: 1.65 $
$Author: kohlere $
$Date: 1999/05/19 18:23:35 $
$State: Exp $
$Source: /home/lefurgy/tmp/ISC-repository/isc/hardware/ARM10/behavioral/arm10.v,v $
*****************************************************************************/

module arm10(GCLK, nRESET, BIGEND, CHSD, CHSE, LATECANCEL, PASS, InM);

/*------------------------------------------------------------------------
        Ports
------------------------------------------------------------------------*/
input nRESET;		//reset input signal
input GCLK;		//clock input signal
input BIGEND;		//Memory in Big Endian Format if High
input [1:0] CHSD;	//Coprocessor Decode Stage Handshake
input [1:0] CHSE;	//Coprocessor Execute Stage Handshake
output LATECANCEL;	//Coprocessor Late Cancel
output PASS;		//Coprocessor Pass
output [4:0] InM;	//Processor Mode Bits

/*------------------------------------------------------------------------
        Defines
------------------------------------------------------------------------*/
`define USR  (5'b10000)		//User Mode
`define FIQ  (5'b10001)		//FIQ Mode
`define IRQ  (5'b10010)		//IRQ Mode
`define SVC  (5'b10011)		//Supervisor Mode
`define ABT  (5'b10111)		//Abort Mode
`define UND  (5'b11011)		//Undefined Mode
`define SYS  (5'b11111)		//System Mode

`define EQ   (4'b0000)		//Z set		  => equal
`define NE   (4'b0001)          //Z clear 	  => not equal
`define CS   (4'b0010)          //C set   	  => unsigned higher or same 
`define CC   (4'b0011)          //C clear	  => unsigned lower
`define MI   (4'b0100)          //N set		  => negative
`define PL   (4'b0101)          //N clear	  => positive or zero
`define VS   (4'b0110)          //V set		  => overflow
`define VC   (4'b0111)          //V clear	  => no overflow
`define HI   (4'b1000)          //C set & Z clear => unsigned higher
`define LS   (4'b1001)          //C clear | Z set => unsigend lower or same
`define GE   (4'b1010)          //N equals V	  => greater or equal
`define LT   (4'b1011)          //N not equal V	  => less than
`define GT   (4'b1100)          //Z clear & (N=Z) => greater than
`define LE   (4'b1101)          //Z set | (N!=Z)  => less than or equal
`define AL   (4'b1110)          //(ignored)	  => always

`define AND  (4'b0000)		//ALU opcode AND
`define EOR  (4'b0001) 		//ALU opcode Exclusive-OR
`define SUB  (4'b0010)		//ALU opcode Subtract (Rd = Rn - Op2)
`define RSB  (4'b0011)		//ALU opcode Reverse Subtract (Rd = Op2 - Rn)
`define ADD  (4'b0100)		//ALU opcode ADD
`define ADC  (4'b0101)		//ALU opcode ADD with Carry
`define SBC  (4'b0110)		//ALU opcode Subtract with Carry
`define RSC  (4'b0111)		//ALU opcode Reverse Subtract with Carry
`define TST  (4'b1000)		//ALU opcode Test Bits
`define TEQ  (4'b1001)		//ALU opcode Test Bitwise Equality
`define CMP  (4'b1010)		//ALU opcode Compare
`define CMN  (4'b1011)		//ALU opcode Compare Negative
`define ORR  (4'b1100) 		//ALU opcode OR
`define MOV  (4'b1101) 		//ALU opcode Move Register or Constant
`define BIC  (4'b1110) 		//ALU opcode Bit Clear
`define MVN  (4'b1111) 		//ALU opcode Move Negative Register

/*------------------------------------------------------------------------
        Machine Component Declarations
------------------------------------------------------------------------*/
//Memory State
	reg [31:0] mem [65536:0];		//primary memory

//Processor State
	reg [31:0] PSR5, PSR4, PSR3, PSR2;	//Program Status Registers 
	reg [31:0] PSR1, PSR0;

//Register File
	reg [31:0] r0, r1, r2, r3, r4;		
	reg [31:0] r5, r6, r7, r8, r9;
        reg [31:0] r10, r11, r12, r13, r14;
        reg [31:0] r15, r16, r17, r18, r19;
        reg [31:0] r20, r21, r22, r23, r24;
        reg [31:0] r25, r26, r27, r28, r29;
        reg [31:0] r30, next_pc;


//Simple Declarations
	reg  	    pc_touched;			//Load next_pc;
	reg	    LATECANCEL;			//Signal to Coprocessor
	reg	    PASS;			//Signal to Coprocessor
	reg  [31:0] addr_bus;			//Address Bus Data Memory
	reg  [31:0] data_bus;			//Data Bus Data Memory
	wire [31:0] PC = r15;			//Program Counter (next)
	reg  [31:0] inst_result [15:0];		//Results of Instruction
	reg  [4:0]  result_dest [15:0];		//Destination of inst_result
	reg  [15:0] result_valid;		//Result is valid, writable
	reg  [31:0] psr_result [1:0];		//Result to be written to CPSR/SPSR
	reg  [2:0]  psr_dest [1:0];		//Destination for PSR result
	reg  [1:0]  psr_valid;			//Result for PSR Valid

	wire [31:0] CPSR = PSR0;		//Current PSR
	wire [31:0] SPSR_fiq = PSR1;		//Saved PSR in FIQ mode
	wire [31:0] SPSR_svc = PSR2;		//Saved PSR in SVC mode
	wire [31:0] SPSR_abt = PSR3;		//Saved PSR in ABT mode
	wire [31:0] SPSR_irq = PSR4;		//Saved PSR in IRQ mode
	wire [31:0] SPSR_und = PSR5;		//Saved PSR in UND mode

	wire N = CPSR[31];			//Negative / Less-Than
	wire Z = CPSR[30];			//Zero / Equal
	wire C = CPSR[29];			//Carry / Borrow / Extend
	wire V = CPSR[28];			//Overflow
	wire I = CPSR[7];			//IRQ Disable
	wire F = CPSR[6];			//FIQ Disable
	wire T = CPSR[5];			//Thumb State Bit
	wire [4:0] MODE = CPSR[4:0];		//Mode Bits	
	wire [4:0] InM = CPSR[4:0];		//Instruction Mode
	
//Instruction Format
	reg  [31:0] ir;				//instruction
	wire [3:0] opcode = ir[24:21];		//opcode for DP insts
	wire [3:0] cond = ir[31:28];		//conditions
	wire [3:0] Rm = ir[3:0];		//Operand 2
	wire [3:0] Rd = ir[15:12];		//Destination Reg
	wire [3:0] Rn = ir[19:16];		//Operand 1
	wire [3:0] Rs = ir[11:8];		//Shift Register
	wire [2:0] TYPE = ir[27:25];		//Type of Instruction
	wire       S = ir[20];			//Set Condition Codes
	wire 	   Imm = ir[25];		//Operand 2 is Immediate

initial
begin
	r0 = 32'h00000000;
        r1 = 32'h00000000;
        r2 = 32'h00000000;
        r3 = 32'h00000000;
        r4 = 32'h00000000;
        r5 = 32'h00000000;
        r6 = 32'h00000000;
        r7 = 32'h00000000;
        r8 = 32'h00000000;
        r9 = 32'h00000000;
        r10 = 32'h00000000;
        r11 = 32'h00000000;
        r12 = 32'h00000000;
        r13 = 32'h00000000;
        r14 = 32'h00000000;
        r15 = 32'h00000000;
        r16 = 32'h00000000;
        r17 = 32'h00000000;
        r18 = 32'h00000000;
        r19 = 32'h00000000;
        r20 = 32'h00000000;
        r21 = 32'h00000000;
        r22 = 32'h00000000;
        r23 = 32'h00000800;
        r24 = 32'h00000000;
        r25 = 32'h00000800;
        r26 = 32'h00000000;
        r27 = 32'h00000000;
        r28 = 32'h00000000;
        r29 = 32'h00000800;
	r30 = 32'h00000000;
	PSR0 = 32'h00000010;
        PSR1 = 32'h00000000;
        PSR2 = 32'h00000000;
        PSR3 = 32'h00000000;
        PSR4 = 32'h00000000;
        PSR5 = 32'h00000000;
	ir = mem[r15[31:2]];
	next_pc = 32'h00000000;
	pc_touched = 1'b1;
	result_valid = 16'h0000;
	psr_valid = 2'h0;
	
end

/*------------------------------------------------------------------------
        Behavioral Blocks
------------------------------------------------------------------------*/
//Fetch Instruction and Increment PC
	always @(posedge GCLK)
		begin
		    if (pc_touched == 1'b1)
		    begin
			r15 = next_pc;		//Load PC
			pc_touched = 1'b0;
		    end
		    else
		        r15 = r15 + 4;		//Increment PC

		    ir = mem[r15[31:2]];	//Load Next Inst
		end

//Perform a Reset on PC, Condition Codes, and Register File
	always @(nRESET or GCLK)
		begin
			if (!nRESET)
			begin
			    r24 = PC;	            //copy PC to R14_svc
			    PSR2 = CPSR;	    //copy CPSR to SPSR_svc
			    next_pc = 32'h00000000; //set PC to 0
			    pc_touched = 1'b1;	    //load PC--don't increment
			    PSR0 = 32'h000000D3;    //Set CPSR to SVC mode
			    PASS = 1'b0;	    //Coprocessor Signal reset
			    LATECANCEL = 1'b0;	    //Coprocessor Signal reset
			end
		end

//Write Result of Instruction if Valid
	always @(negedge GCLK) #49 write_result;

	task write_result;
	integer z;
	    begin
		for (z=0; z < 16; z=z+1)
		  begin
		    if (result_valid[z])
		      begin
			result_valid[z] = 1'b0;
  		        write_reg(result_dest[z], inst_result[z]);
		      end
		  end
	    end
	endtask

//Commit PSR Changes
	always @(posedge GCLK) commit_psr;

	task commit_psr;
	integer y;
	    begin
		for (y = 0; y < 2; y=y+1)
		  begin
		    if (psr_valid[y])
		      begin
		        write_psr(psr_dest[y], psr_result[y]);
		        psr_valid[y] = 1'b0;
		      end
		  end
	    end
	endtask

//Execute Instruction and latch results on Rising edge of GCLK
	always @(posedge GCLK)
	    begin
		#5;
                if (eval_cond(cond) == 1'b1) begin
		case (ir[27:20])
		    8'h00: 
		    begin
		        if (ir[11:4] == 8'h0B) 
                // STRH register offset, no write-back, down, post indexed 
			    strh;
			else if (ir[7:4] == 4'h9)
		// MUL Instruction
			    mul;
			else
		// AND -- 2nd Operand a Register
			    alu;
                    end

		    8'h01: 
		    begin    
			if (ir[7:4] == 4'h9)
		// MULS Instruction
			    mul;
                        else if ((ir[11:4] & 8'hF9) == 8'h09)
                // LDRHSB register offset, no write-back, down, post indexed
                            ldrh;
			else
		// ANDS -- 2nd Operand a Register
			    alu;
		    end

		    8'h02:
		    begin
			if (ir[11:4] == 8'h0B)
		// STRH register offset, write-back, down, post indexed
			    strh;
			else if (ir[7:4] == 4'h9)
		// MLA Instruction
			    mul;
			else
		// EOR Instruction -- 2nd Operand a Register
			    alu;
		    end

		    8'h03:
		    begin
                        if (ir[7:4] == 4'h9)
                // MLAS Instruction
                            mul;   
                        else if ((ir[11:4] & 8'hF9) == 8'h09)
		// LDRHSB register offset, write-back, down, post indexed
			    ldrh;
			else
		// EORS Instruction -- 2nd Operand a Regiseter
			    alu;
		    end

		    8'h04:
		    begin
			if (ir[7:4] == 4'hB)
		// STRH immediate offset, no write-back, down, post indexed
			    strh;
			else
		// SUB Instruction -- 2nd Operand a Register
			    alu;
		    end

		    8'h05:
		    begin
                        if ((ir[11:4] & 8'h09) == 8'h09)
		// LDRHSB immediate offset, no write-back, down, post indexed
			    ldrh;
			else
		// SUBS Instruction -- 2nd Operand a Register
			    alu;
		    end

		    8'h06:
		    begin
			if (ir[7:4] == 4'hB)
		// STRH immediate offset, write-back, down, post indexed
			    strh;
			else
		// RSB Instruction
			    alu;
		    end

		    8'h07:
		    begin
                        if ((ir[11:4] & 8'h09) == 8'h09)
                // LDRHSB immediate offset, write-back, down, post indexed
			    ldrh;
			else
		// RSBS Instruction -- 2nd Operand a Register
			    alu;
		    end
	
		    8'h08:
		    begin
			if (ir[11:4] == 8'h0B)
		// STRH register offset, no write-back, up, post indexed
			    strh;
			else if (ir[7:4] == 4'h9)
		// UMULL Instruction
			    mull;
			else
		// ADD Instruction -- 2nd Operand a Register
			    alu;
		    end


		    8'h09:
		    begin
                        if (ir[7:4] == 4'h9)
                // UMULLS Instruction  
			    mull;
                        else if ((ir[11:4] & 8'hF9) == 8'h09)
		// LDRHSB register offset, no write-back, up, post indexed
			    ldrh;
			else
		// ADDS Instruction -- 2nd Operand a Register
			    alu;
		    end

		    8'h0A:
		    begin
			if (ir[11:4] == 8'h0B)
		// STRH register offset, write-back, up, post indexed
			    strh;
			else if (ir[7:4] == 4'h9)
		// UMLAL Instruction
			    mull;
			else
		// ADC Instruction -- 2nd Operand a Register
			    alu;
		    end

		    8'h0B:
		    begin
                        if (ir[7:4] == 4'h9)
                // UMLALS Instruction  
			    mull;
                        else if ((ir[11:4] & 8'hF9) == 8'h09)
		// LDRHSB register offset, write-back, up, post indexed
			    ldrh;
			else
		// ADCS Instruction -- 2nd Operand a Register
			    alu;
		    end

		    8'h0C:
		    begin
			if (ir[7:4] == 4'hB)
		// STRH immediate offset, no write-back, up post indexed
			    strh;
			else if (ir[7:4] == 4'h9)
		// SMULL Instruction
			    mull;
			else
		// SBC Instruction -- 2nd Operand a Register
			    alu;
		    end

		    8'h0D:
		    begin
                        if (ir[7:4] == 4'h9)
		// SMULLS Instrcution
			    mull;
                        else if ((ir[11:4] & 8'h09) == 8'h09)
                // LDRHSB immediate offset, no write-back, up, post indexed
			    ldrh;
			else
		// SBCS Instruction -- 2nd Operand a Register
			    alu;
		    end
		
		    8'h0E:
		    begin
			if (ir[7:4] == 4'hB)
                // STRH immediate offset, write-back, up post indexed
                            strh;
                        else if (ir[7:4] == 4'h9)
                // SMLAL Instruction
                             mull;