simcon.v

arm10_verilog.rar是基于arm10的verilog代码

/*-----------------------------------------------------------------------------
Module:		simcon
Author:		Scott Venier
Filename:	simcon.v
Description:	simulator interface to the behavioral model of the ARM10
		(arm10.v)
-----------------------------------------------------------------------------*/

`define SAVE_INTERVAL	 10000000

module simcon();

integer		instruction_count;
integer		instr_limit;
integer		next_checkpoint;
integer		timer;
integer		timeout;

reg		save_enable;

task processargs;
begin

	/* make a trn file for signalscan */
	if($test$plusargs("trn"))
	begin
		$recordfile("arm.trn");
		$recordvars;
	end

	/* if this is a restart then append to dump file */
	if($test$plusargs("restart"))
	begin
		$reopen("arm_reg.dump");
		$init_sim(".rsim",instr_limit,next_checkpoint,timeout);
	end

	if($test$plusargs("verify"))
	begin
		$init_verify();
	end

	/* enable save capability */
	if($test$plusargs("save")) save_enable = 1;
	else save_enable = 0;

end
endtask

initial
begin
	instruction_count=0;
	timer=0;
	next_checkpoint=1;
	$init_sim(".isim",instr_limit,next_checkpoint,timeout);
	processargs;
        $init_state(".istate","arm_reg.dump");
end

always #`SAVE_INTERVAL
begin
	if(save_enable)
	begin
		$system("/bin/mv -f save save.1");
		$save("save");
	/*	#0 processargs */
	end
end

//always @(test_arm.nRESET)
//begin
//	$init_state(".istate","arm_reg.dump");
//end

always @(instruction_count or next_checkpoint or timer or timeout)
begin
	if(instruction_count==next_checkpoint || instruction_count>=instr_limit ||
	    timer>=timeout)
		$check_state(instruction_count,next_checkpoint,instr_limit,timer,
		    timeout);
end

always @(test_arm.GCLK)
begin
	if(test_arm.GCLK==1)
	begin
		timer=timer+1;
		instruction_count=instruction_count+1;
	end
end

endmodule /* simcon */