clock_if_entarch.vhd

arm9_fpga2_verilog是一个可以综合的用verilog写的arm9的ip软核

  --  Clock Delay Locked Loops (CLKDLL)
  --
  ----------------------------------------------------------------------

  G_NO_M_DLL : if ( M_CLK_DLL_TYPE = NONE ) generate
    M_CLK_0 <= Clock_In.M_Clk;
    User_In.M_Clk_Locked <= '1';
  end generate G_NO_M_DLL;

  G_LF_M_DLL : if ( M_CLK_DLL_TYPE = LOW_FREQ ) generate
    attribute STARTUP_WAIT of U_M_CLK_DLL : label is "FALSE";
    attribute DUTY_CYCLE_CORRECTION of U_M_CLK_DLL : label is "FALSE";
    attribute CLKDV_DIVIDE of U_M_CLK_DLL : label is "2.0";
  begin
    U_M_CLK_DLL : CLKDLL
      -- synopsys synthesis_off
      generic map
      (
        DUTY_CYCLE_CORRECTION => FALSE,
        CLKDV_DIVIDE          => 2.0
      )
      -- synopsys synthesis_on
      port map
      (
        CLKIN   => Clock_In.M_Clk,
        CLKFB   => M_CLK_FB,
        RST     => M_CLK_RST,
        CLK0    => M_CLK_0,
        CLK90   => M_CLK_90,
        CLK180  => M_CLK_180,
        CLK270  => M_CLK_270,
        CLK2X   => M_CLK_2X,
        CLKDV   => M_CLK_DV,
        LOCKED  => User_In.M_Clk_Locked
      );
  end generate G_LF_M_DLL;

  G_HF_M_DLL : if ( M_CLK_DLL_TYPE = HIGH_FREQ ) generate
    attribute STARTUP_WAIT of U_M_CLK_DLL : label is "FALSE";
    attribute DUTY_CYCLE_CORRECTION of U_M_CLK_DLL : label is "FALSE";
    attribute CLKDV_DIVIDE of U_M_CLK_DLL : label is "2.0";
  begin
    U_M_CLK_DLL : CLKDLLHF
      -- synopsys synthesis_off
      generic map
      (
        DUTY_CYCLE_CORRECTION => FALSE,
        CLKDV_DIVIDE          => 2.0
      )
      -- synopsys synthesis_on
      port map
      (
        CLKIN   => Clock_In.M_Clk,
        CLKFB   => M_CLK_FB,
        RST     => M_CLK_RST,
        CLK0    => M_CLK_0,
        CLK180  => M_CLK_180,
        CLKDV   => M_CLK_DV,
        LOCKED  => User_In.M_Clk_Locked
      );
  end generate G_HF_M_DLL;

  G_NO_P_DLL : if ( P_CLK_DLL_TYPE = NONE ) generate
    P_CLK_0 <= Clock_In.P_Clk;
    User_In.P_Clk_Locked <= '1';
  end generate G_NO_P_DLL;

  G_LF_P_DLL : if ( P_CLK_DLL_TYPE = LOW_FREQ ) generate
    attribute STARTUP_WAIT of U_P_CLK_DLL : label is "FALSE";
    attribute DUTY_CYCLE_CORRECTION of U_P_CLK_DLL : label is "FALSE";
    attribute CLKDV_DIVIDE of U_P_CLK_DLL : label is "2.0";
  begin
    U_P_CLK_DLL : CLKDLL
      -- synopsys synthesis_off
      generic map
      (
        DUTY_CYCLE_CORRECTION => FALSE,
        CLKDV_DIVIDE          => 2.0
      )
      -- synopsys synthesis_on
      port map
      (
        CLKIN   => Clock_In.P_Clk,
        CLKFB   => P_CLK_FB,
        RST     => P_CLK_RST,
        CLK0    => P_CLK_0,
        CLK90   => P_CLK_90,
        CLK180  => P_CLK_180,
        CLK270  => P_CLK_270,
        CLK2X   => P_CLK_2X,
        CLKDV   => P_CLK_DV,
        LOCKED  => User_In.P_Clk_Locked
      );
  end generate G_LF_P_DLL;

  G_HF_P_DLL : if ( P_CLK_DLL_TYPE = HIGH_FREQ ) generate
    attribute STARTUP_WAIT of U_P_CLK_DLL : label is "FALSE";
    attribute DUTY_CYCLE_CORRECTION of U_P_CLK_DLL : label is "FALSE";
    attribute CLKDV_DIVIDE of U_P_CLK_DLL : label is "2.0";
  begin
    U_P_CLK_DLL : CLKDLLHF
      -- synopsys synthesis_off
      generic map
      (
        DUTY_CYCLE_CORRECTION => FALSE,
        CLKDV_DIVIDE          => 2.0
      )
      -- synopsys synthesis_on
      port map
      (
        CLKIN   => Clock_In.P_Clk,
        CLKFB   => P_CLK_FB,
        RST     => P_CLK_RST,
        CLK0    => P_CLK_0,
        CLK180  => P_CLK_180,
        CLKDV   => P_CLK_DV,
        LOCKED  => User_In.P_Clk_Locked
      );
  end generate G_HF_P_DLL;

  U_K_CLK_DLL : CLKDLL
    -- synopsys synthesis_off
    generic map
    (
      DUTY_CYCLE_CORRECTION => FALSE,
      CLKDV_DIVIDE          => 2.0
    )
    -- synopsys synthesis_on
    port map
    (
      CLKIN   => Clock_In.K_Clk,
      CLKFB   => K_CLK_FB,
      RST     => K_CLK_RST,
      CLK0    => K_CLK_0,
      CLK90   => K_CLK_90,
      CLK180  => K_CLK_180,
      CLK270  => K_CLK_270,
      CLK2X   => K_CLK_2X,
      CLKDV   => K_CLK_DV,
      LOCKED  => User_In.K_Clk_Locked
    );

  G_NO_U_DLL : if ( U_CLK_DLL_TYPE = NONE ) generate
    U_CLK_0 <= Clock_In.U_Clk;
    User_In.U_Clk_Locked <= '1';
  end generate G_NO_U_DLL;

  G_LF_U_DLL : if ( U_CLK_DLL_TYPE = LOW_FREQ ) generate
    attribute STARTUP_WAIT of U_U_CLK_DLL : label is "FALSE";
    attribute DUTY_CYCLE_CORRECTION of U_U_CLK_DLL : label is "FALSE";
    attribute CLKDV_DIVIDE of U_U_CLK_DLL : label is "2.0";
  begin
    U_U_CLK_DLL : CLKDLL
      -- synopsys synthesis_off
      generic map
      (
        DUTY_CYCLE_CORRECTION => FALSE,
        CLKDV_DIVIDE          => 2.0
      )
      -- synopsys synthesis_on
      port map
      (
        CLKIN   => Clock_In.U_Clk,
        CLKFB   => U_CLK_FB,
        RST     => U_CLK_RST,
        CLK0    => U_CLK_0,
        CLK90   => U_CLK_90,
        CLK180  => U_CLK_180,
        CLK270  => U_CLK_270,
        CLK2X   => U_CLK_2X,
        CLKDV   => U_CLK_DV,
        LOCKED  => User_In.U_Clk_Locked
      );
  end generate G_LF_U_DLL;

  G_HF_U_DLL : if ( U_CLK_DLL_TYPE = HIGH_FREQ ) generate
    attribute STARTUP_WAIT of U_U_CLK_DLL : label is "FALSE";
    attribute DUTY_CYCLE_CORRECTION of U_U_CLK_DLL : label is "FALSE";
    attribute CLKDV_DIVIDE of U_U_CLK_DLL : label is "2.0";
  begin
    U_U_CLK_DLL : CLKDLLHF
      -- synopsys synthesis_off
      generic map
      (
        DUTY_CYCLE_CORRECTION => FALSE,
        CLKDV_DIVIDE          => 2.0
      )
      -- synopsys synthesis_on
      port map
      (
        CLKIN   => Clock_In.U_Clk,
        CLKFB   => U_CLK_FB,
        RST     => U_CLK_RST,
        CLK0    => U_CLK_0,
        CLK180  => U_CLK_180,
        CLKDV   => U_CLK_DV,
        LOCKED  => User_In.U_Clk_Locked
      );
  end generate G_HF_U_DLL;

  ----------------------------------------------------------------------
  --
  --  Global clock buffers
  --
  ----------------------------------------------------------------------

  U_M_CLK : BUFG
    port map
    (
      I => M_CLK_0,
      O => M_CLK_FB
    );

  U_P_CLK : BUFG
    port map
    (
      I => P_CLK_0,
      O => P_CLK_FB
    );

  U_K_CLK : BUFG
    port map
    (
      I => K_CLK_0,
      O => K_CLK_FB
    );

  U_U_CLK : BUFG
    port map
    (
      I => U_CLK_0,
      O => U_CLK_FB
    );

end Standard;