clock_if_entarch.vhd

arm9_fpga2_verilog是一个可以综合的用verilog写的arm9的ip软核

------------------------------------------------------------------------
--
--  Copyright (C) 1998-1999, Annapolis Micro Systems, Inc.
--  All Rights Reserved.
--
------------------------------------------------------------------------

------------------------------------------------------------------------
--
--  Entity        : Clock_Std_IF
--
--  Architecture  : Standard
--
--  Filename      : clock_if_entarch.vhd
--
--  Date          : 9/3/99
--
--  Description   : Models a standard interface to the clock resources
--                  of the PEX.
--
------------------------------------------------------------------------

------------------------------- Glossary -------------------------------
--
--  Name Key:
--  =========
--  _AS       : Address Strobe
--  _CE       : Clock Enable
--  _CS       : Chip Select
--  _DS       : Data Strobe
--  _EN       : Enable
--  _OE       : Output Enable
--  _RD       : Read Select
--  _WE       : Write Enable
--  _WR       : Write Select
--  _d[d...]  : Delayed (registered) signal (each 'd' denotes one 
--              level of delay)
--  _n        : Active low signals (must be last part of name)
--
--  Generic Name                  Description
--  ============================  ======================================
--  M_CLK_DLL_TYPE                Type of CLKDLL to be used for M_Clk:
--                                NONE (below 25 MHz), LOW_FREQ (25 to
--                                90 MHz), or HIGH_FREQ (60 to 180 MHz).
--  P_CLK_DLL_TYPE                Type of CLKDLL to be used for P_Clk:
--                                NONE (below 25 MHz), LOW_FREQ (25 to
--                                90 MHz), or HIGH_FREQ (60 to 180 MHz).
--  U_CLK_DLL_TYPE                Type of CLKDLL to be used for U_Clk:
--                                NONE (below 25 MHz), LOW_FREQ (25 to
--                                90 MHz), or HIGH_FREQ (60 to 180 MHz).
--
--  Port Name                 Width  Dir  Description
--  ====================      =====  ===  ==============================
--  Pads.M_Clk                  1     I   Memory clock
--  Pads.P_Clk                  1     I   Processing element clock
--  Pads.K_Clk                  1     I   LAD-bus clock
--  Pads.U_Clk                  1     I   User clock
--  User_In.M_Clk               1     O   Memory clock
--  User_In.P_Clk               1     O   Processing element clock
--  User_In.K_Clk               1     O   LAD-bus clock
--  User_In.U_Clk               1     O   User clock
--  User_In.M_Clk_Locked        1     O   M_Clk CLKDLL locked flag
--  User_In.P_Clk_Locked        1     O   P_Clk CLKDLL locked flag
--  User_In.K_Clk_Locked        1     O   K_Clk CLKDLL locked flag
--  User_In.U_Clk_Locked        1     O   U_Clk CLKDLL locked flag
--
------------------------------------------------------------------------

-------------------------- Library Declarations ------------------------

library IEEE, PEX_Lib, SYSTEM;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use PEX_Lib.PE_Package.all;
use SYSTEM.Xilinx_Package.all;

--------------------------- Entity Declaration -------------------------

entity Clock_Std_IF is
  generic
  (
    M_CLK_DLL_TYPE  : INTEGER := LOW_FREQ;
    P_CLK_DLL_TYPE  : INTEGER := LOW_FREQ;
    U_CLK_DLL_TYPE  : INTEGER := LOW_FREQ
  );
  port
  (
    Pads    : inout Clock_Pads_Type;
    User_In :   out Clock_Std_IF_In_Type
  );
end Clock_Std_IF;
 
------------------------ Architecture Declaration ----------------------

architecture Standard of Clock_Std_IF is

  ------------------------------- Glossary -----------------------------
  --
  --  Name Key:
  --  =========
  --  _AS       : Address Strobe
  --  _CE       : Clock Enable
  --  _CS       : Chip Select
  --  _DS       : Data Strobe
  --  _EN       : Enable
  --  _OE       : Output Enable
  --  _RD       : Read Select
  --  _WE       : Write Enable
  --  _WR       : Write Select
  --  _d[d...]  : Delayed (registered) signal (each 'd' denotes one 
  --              level of delay)
  --  _n        : Active low signals (must be last part of name)
  --
  --  Signal Name                   Description
  --  ============================  ====================================
  --  Clock_In.M_Clk                Memory clock
  --  Clock_In.P_Clk                Processing element clock
  --  Clock_In.K_Clk                LAD-bus clock
  --  Clock_In.U_Clk                User clock
  --  M_CLK_FB                      M_Clk CLKDLL feedback clock
  --  M_CLK_RST                     M_Clk CLKDLL reset signal
  --  M_CLK_0                       M_Clk CLKDLL 0 degree phase clock
  --  M_CLK_90                      M_Clk CLKDLL 90 degree phase clock
  --  M_CLK_180                     M_Clk CLKDLL 180 degree phase clock
  --  M_CLK_270                     M_Clk CLKDLL 270 degree phase clock
  --  M_CLK_2X                      M_Clk CLKDLL 2x clock
  --  M_CLK_DV                      M_Clk CLKDLL divided clock
  --  P_CLK_FB                      P_Clk CLKDLL feedback clock
  --  P_CLK_RST                     P_Clk CLKDLL reset signal
  --  P_CLK_0                       P_Clk CLKDLL 0 degree phase clock
  --  P_CLK_90                      P_Clk CLKDLL 90 degree phase clock
  --  P_CLK_180                     P_Clk CLKDLL 180 degree phase clock
  --  P_CLK_270                     P_Clk CLKDLL 270 degree phase clock
  --  P_CLK_2X                      P_Clk CLKDLL 2x clock
  --  P_CLK_DV                      P_Clk CLKDLL divided clock
  --  K_CLK_FB                      K_Clk CLKDLL feedback clock
  --  K_CLK_RST                     K_Clk CLKDLL reset signal
  --  K_CLK_0                       K_Clk CLKDLL 0 degree phase clock
  --  K_CLK_90                      K_Clk CLKDLL 90 degree phase clock
  --  K_CLK_180                     K_Clk CLKDLL 180 degree phase clock
  --  K_CLK_270                     K_Clk CLKDLL 270 degree phase clock
  --  K_CLK_2X                      K_Clk CLKDLL 2x clock
  --  K_CLK_DV                      K_Clk CLKDLL divided clock
  --  U_CLK_FB                      U_Clk CLKDLL feedback clock
  --  U_CLK_RST                     U_Clk CLKDLL reset signal
  --  U_CLK_0                       U_Clk CLKDLL 0 degree phase clock
  --  U_CLK_90                      U_Clk CLKDLL 90 degree phase clock
  --  U_CLK_180                     U_Clk CLKDLL 180 degree phase clock
  --  U_CLK_270                     U_Clk CLKDLL 270 degree phase clock
  --  U_CLK_2X                      U_Clk CLKDLL 2x clock
  --  U_CLK_DV                      U_Clk CLKDLL divided clock
  --
  --  Attribute Name                  Description
  --  ==============================  ==================================
  --  STARTUP_WAIT                    Component string attribute that
  --                                  when TRUE causes the DONE signal
  --                                  to be delayed during configuration 
  --                                  until the CLKDLL has gained a 
  --                                  lock.
  --  DUTY_CYCLE_CORRECTION           Component string attribute that
  --                                  when true causes the CLKDLL to
  --                                  correct the duty cycle of its
  --                                  output clock to be a 50% duty
  --                                  cycle.
  --  CLKDV_DIVIDE                    Component string attribute that
  --                                  indicates the amount the CLKDLL
  --                                  is to divide the CLKIN signal to
  --                                  produce the CLKDV signal.
  --
  ----------------------------------------------------------------------
  signal Clock_In : Clock_Basic_IO_In_Type;
  signal M_CLK_FB : std_logic;
  signal M_CLK_RST : std_logic;
  signal M_CLK_0 : std_logic;
  signal M_CLK_90 : std_logic;
  signal M_CLK_180 : std_logic;
  signal M_CLK_270 : std_logic;
  signal M_CLK_2X : std_logic;
  signal M_CLK_DV : std_logic;
  signal P_CLK_FB : std_logic;
  signal P_CLK_RST : std_logic;
  signal P_CLK_0 : std_logic;
  signal P_CLK_90 : std_logic;
  signal P_CLK_180 : std_logic;
  signal P_CLK_270 : std_logic;
  signal P_CLK_2X : std_logic;
  signal P_CLK_DV : std_logic;
  signal K_CLK_FB : std_logic;
  signal K_CLK_RST : std_logic;
  signal K_CLK_0 : std_logic;
  signal K_CLK_90 : std_logic;
  signal K_CLK_180 : std_logic;
  signal K_CLK_270 : std_logic;
  signal K_CLK_2X : std_logic;
  signal K_CLK_DV : std_logic;
  signal U_CLK_FB : std_logic;
  signal U_CLK_RST : std_logic;
  signal U_CLK_0 : std_logic;
  signal U_CLK_90 : std_logic;
  signal U_CLK_180 : std_logic;
  signal U_CLK_270 : std_logic;
  signal U_CLK_2X : std_logic;
  signal U_CLK_DV : std_logic;

  attribute STARTUP_WAIT : string;
  attribute DUTY_CYCLE_CORRECTION : string;
  attribute CLKDV_DIVIDE : string;

  attribute STARTUP_WAIT of U_K_CLK_DLL : label is "FALSE";
  attribute DUTY_CYCLE_CORRECTION of U_K_CLK_DLL : label is "FALSE";
  attribute CLKDV_DIVIDE of U_K_CLK_DLL : label is "2.0";

begin

  Init_Clock_Std_IF ( User_In );
  Init_Clock_Basic_IO ( Clock_In );

  M_CLK_RST <= '0';
  P_CLK_RST <= '0';
  K_CLK_RST <= '0';
  U_CLK_RST <= '0';

  User_In.M_Clk <= M_CLK_FB;
  User_In.P_Clk <= P_CLK_FB;
  User_In.K_Clk <= K_CLK_FB;
  User_In.U_Clk <= U_CLK_FB;

  U_Clock_Basic_IO : Clock_Basic_IO
    port map
    (
      Pads    => Pads,
      User_In => Clock_In
    );

  ----------------------------------------------------------------------
  --