lad_bus_io_entarch.vhd

arm9_fpga2_verilog是一个可以综合的用verilog写的arm9的ip软核

    U_Addr_Data_In_12 : IBUF
      port map
      (
        I => Pads.Addr_Data(12),
        O => User_In.Addr_Data_In(12)
      );

    U_Data_Out_13 : OBUFT
      port map
      (
        O => Pads.Addr_Data(13),
        I => User_Out.Addr_Data_Out(13),
        T => User_Out.Addr_Data_OE_n(13)
      );

    U_Addr_Data_In_13 : IBUF
      port map
      (
        I => Pads.Addr_Data(13),
        O => User_In.Addr_Data_In(13)
      );

    U_Data_Out_14 : OBUFT
      port map
      (
        O => Pads.Addr_Data(14),
        I => User_Out.Addr_Data_Out(14),
        T => User_Out.Addr_Data_OE_n(14)
      );

    U_Addr_Data_In_14 : IBUF
      port map
      (
        I => Pads.Addr_Data(14),
        O => User_In.Addr_Data_In(14)
      );

    U_Data_Out_15 : OBUFT
      port map
      (
        O => Pads.Addr_Data(15),
        I => User_Out.Addr_Data_Out(15),
        T => User_Out.Addr_Data_OE_n(15)
      );

    U_Addr_Data_In_15 : IBUF
      port map
      (
        I => Pads.Addr_Data(15),
        O => User_In.Addr_Data_In(15)
      );

    U_Data_Out_16 : OBUFT
      port map
      (
        O => Pads.Addr_Data(16),
        I => User_Out.Addr_Data_Out(16),
        T => User_Out.Addr_Data_OE_n(16)
      );

    U_Addr_Data_In_16 : IBUF
      port map
      (
        I => Pads.Addr_Data(16),
        O => User_In.Addr_Data_In(16)
      );

    U_Data_Out_17 : OBUFT
      port map
      (
        O => Pads.Addr_Data(17),
        I => User_Out.Addr_Data_Out(17),
        T => User_Out.Addr_Data_OE_n(17)
      );

    U_Addr_Data_In_17 : IBUF
      port map
      (
        I => Pads.Addr_Data(17),
        O => User_In.Addr_Data_In(17)
      );

    U_Data_Out_18 : OBUFT
      port map
      (
        O => Pads.Addr_Data(18),
        I => User_Out.Addr_Data_Out(18),
        T => User_Out.Addr_Data_OE_n(18)
      );

    U_Addr_Data_In_18 : IBUF
      port map
      (
        I => Pads.Addr_Data(18),
        O => User_In.Addr_Data_In(18)
      );

    U_Data_Out_19 : OBUFT
      port map
      (
        O => Pads.Addr_Data(19),
        I => User_Out.Addr_Data_Out(19),
        T => User_Out.Addr_Data_OE_n(19)
      );

    U_Addr_Data_In_19 : IBUF
      port map
      (
        I => Pads.Addr_Data(19),
        O => User_In.Addr_Data_In(19)
      );

    U_Data_Out_20 : OBUFT
      port map
      (
        O => Pads.Addr_Data(20),
        I => User_Out.Addr_Data_Out(20),
        T => User_Out.Addr_Data_OE_n(20)
      );

    U_Addr_Data_In_20 : IBUF
      port map
      (
        I => Pads.Addr_Data(20),
        O => User_In.Addr_Data_In(20)
      );

    U_Data_Out_21 : OBUFT
      port map
      (
        O => Pads.Addr_Data(21),
        I => User_Out.Addr_Data_Out(21),
        T => User_Out.Addr_Data_OE_n(21)
      );

    U_Addr_Data_In_21 : IBUF
      port map
      (
        I => Pads.Addr_Data(21),
        O => User_In.Addr_Data_In(21)
      );

    U_Data_Out_22 : OBUFT
      port map
      (
        O => Pads.Addr_Data(22),
        I => User_Out.Addr_Data_Out(22),
        T => User_Out.Addr_Data_OE_n(22)
      );

    U_Addr_Data_In_22 : IBUF
      port map
      (
        I => Pads.Addr_Data(22),
        O => User_In.Addr_Data_In(22)
      );

    U_Data_Out_23 : OBUFT
      port map
      (
        O => Pads.Addr_Data(23),
        I => User_Out.Addr_Data_Out(23),
        T => User_Out.Addr_Data_OE_n(23)
      );

    U_Addr_Data_In_23 : IBUF
      port map
      (
        I => Pads.Addr_Data(23),
        O => User_In.Addr_Data_In(23)
      );

    U_Data_Out_24 : OBUFT
      port map
      (
        O => Pads.Addr_Data(24),
        I => User_Out.Addr_Data_Out(24),
        T => User_Out.Addr_Data_OE_n(24)
      );

    U_Addr_Data_In_24 : IBUF
      port map
      (
        I => Pads.Addr_Data(24),
        O => User_In.Addr_Data_In(24)
      );

    U_Data_Out_25 : OBUFT
      port map
      (
        O => Pads.Addr_Data(25),
        I => User_Out.Addr_Data_Out(25),
        T => User_Out.Addr_Data_OE_n(25)
      );

    U_Addr_Data_In_25 : IBUF
      port map
      (
        I => Pads.Addr_Data(25),
        O => User_In.Addr_Data_In(25)
      );

    U_Data_Out_26 : OBUFT
      port map
      (
        O => Pads.Addr_Data(26),
        I => User_Out.Addr_Data_Out(26),
        T => User_Out.Addr_Data_OE_n(26)
      );

    U_Addr_Data_In_26 : IBUF
      port map
      (
        I => Pads.Addr_Data(26),
        O => User_In.Addr_Data_In(26)
      );

    U_Data_Out_27 : OBUFT
      port map
      (
        O => Pads.Addr_Data(27),
        I => User_Out.Addr_Data_Out(27),
        T => User_Out.Addr_Data_OE_n(27)
      );

    U_Addr_Data_In_27 : IBUF
      port map
      (
        I => Pads.Addr_Data(27),
        O => User_In.Addr_Data_In(27)
      );

    U_Data_Out_28 : OBUFT
      port map
      (
        O => Pads.Addr_Data(28),
        I => User_Out.Addr_Data_Out(28),
        T => User_Out.Addr_Data_OE_n(28)
      );

    U_Addr_Data_In_28 : IBUF
      port map
      (
        I => Pads.Addr_Data(28),
        O => User_In.Addr_Data_In(28)
      );

    U_Data_Out_29 : OBUFT
      port map
      (
        O => Pads.Addr_Data(29),
        I => User_Out.Addr_Data_Out(29),
        T => User_Out.Addr_Data_OE_n(29)
      );

    U_Addr_Data_In_29 : IBUF
      port map
      (
        I => Pads.Addr_Data(29),
        O => User_In.Addr_Data_In(29)
      );

    U_Data_Out_30 : OBUFT
      port map
      (
        O => Pads.Addr_Data(30),
        I => User_Out.Addr_Data_Out(30),
        T => User_Out.Addr_Data_OE_n(30)
      );

    U_Addr_Data_In_30 : IBUF
      port map
      (
        I => Pads.Addr_Data(30),
        O => User_In.Addr_Data_In(30)
      );

    U_Data_Out_31 : OBUFT
      port map
      (
        O => Pads.Addr_Data(31),
        I => User_Out.Addr_Data_Out(31),
        T => User_Out.Addr_Data_OE_n(31)
      );

    U_Addr_Data_In_31 : IBUF
      port map
      (
        I => Pads.Addr_Data(31),
        O => User_In.Addr_Data_In(31)
      );

  U_Reg : IBUF
    port map
    (
      I => Pads.Reg_n,
      O => User_In.Reg_n
    );

  U_WR : IBUF
    port map
    (
      I => Pads.WR_n,
      O => User_In.WR_n
    );

  U_CS : IBUF
    port map
    (
      I => Pads.CS_n,
      O => User_In.CS_n
    );

  U_Int_Req : OBUF
    port map
    (
      O => Pads.Int_Req_n,
      I => User_Out.Int_Req_n
    );

    U_DMA_Chan_0 : IBUF
      port map
      (
        I => Pads.DMA_Chan(0),
        O => User_In.DMA_Chan(0)
      );

    U_DMA_Chan_1 : IBUF
      port map
      (
        I => Pads.DMA_Chan(1),
        O => User_In.DMA_Chan(1)
      );

    U_DMA_Stat_0 : OBUF
      port map
      (
        O => Pads.DMA_Stat(0),
        I => User_Out.DMA_Stat(0)
      );

    U_DMA_Stat_1 : OBUF
      port map
      (
        O => Pads.DMA_Stat(1),
        I => User_Out.DMA_Stat(1)
      );

end Structure;