ex.v

arm9_fpga2_verilog是一个可以综合的用verilog写的arm9的ip软核

//latched on the second cycle if the inst is an MLA/MLAL
//synopsys async_set_reset "nRESET"
always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
        op2 <= 32'h00000000;
    else if (nWAIT)
      begin
	if (~op_disable)
          op2 <= op2_in;
      end
  end

//This block controls the aux data latch
//If an instruction requires 2 cycles, Aux_data is only
//latched on the 2nd cylce if the inst is STR (Reg Offset) or Swap
wire aux_disable = ~(!ex_enbar & (!id_second | (swap | str)));
//synopsys async_set_reset "nRESET"
always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      aux_data_ex <= 32'h00000000;
    else if (nWAIT)
      begin
        if (~aux_disable)
          aux_data_ex <= aux_data_id;
      end
  end

//This block controls the Condition latch
//synopsys async_set_reset "nRESET"
always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      condition <= 4'h0;
    else if (nWAIT)
      begin
        if (~ex_enbar)
          condition <= condition_in; 
      end
  end

//This block controls the second latch
//synopsys async_set_reset "nRESET"
always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      second_ex <= 1'h0;
    else if (nWAIT)
      begin
        if (~ex_enbar)
          second_ex <= id_second;
      end     
  end

//synopsys async_set_reset "nRESET"
always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      need_2cycles_ex <= 1'h0;
    else if (nWAIT)
      begin
        if (~ex_enbar)
          need_2cycles_ex <= need_2cycles_id;
      end
  end


//synopsys async_set_reset "nRESET"
always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      load_use_ex <= 1'h0;
    else if (nWAIT)
      begin
        if (~ex_enbar)
          load_use_ex <= load_use_id;
      end
  end

//This block controls the alu opcode latch
//synopsys async_set_reset "nRESET"
always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      alu_opcode <= 4'h0;
    else if (nWAIT)
      begin
        if (~ex_enbar)
          alu_opcode <= alu_opcode_in; 
      end
  end

//This block controls the shift amount latch
//synopsys async_set_reset "nRESET"
always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      shift_amount <= 8'h00;
    else if (nWAIT)
      begin       
        if (~ex_enbar)
          shift_amount <= shift_amount_in;
      end
  end
       
//This block controls the shift type latch
//synopsys async_set_reset "nRESET"
always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      shift_type <= 3'h0;
    else if (nWAIT)
      begin       
        if (~ex_enbar)
          shift_type <= shift_type_in;
      end
  end 

//This block controls the rdest_1 latch
//synopsys async_set_reset "nRESET"
always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      Rd_ex <= #1 5'h00;
    else if (nWAIT)
      begin
        if (~ex_enbar)
	  begin
	    if (inst_type_in == `MUL)
	      Rd_ex <= #1 Rn_id;
	    else
              Rd_ex <= #1 Rd_id;
	  end
      end
  end

//This block controls the rdest_2 latch 
//synopsys async_set_reset "nRESET"
always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      Rn_ex <= 5'h0;
    else if (nWAIT)
      begin
        if (~ex_enbar)
	  begin
	    if (inst_type_in == `MUL)
	      Rn_ex <= Rd_id;
	    else
	      Rn_ex <= Rn_id;
	  end
      end
  end

//This block controls the multiply latch
//synopsys async_set_reset "nRESET"
always @(posedge nGCLK or negedge nRESET)
  begin
    if (!nRESET)
      inst_type_ex <= 4'h0;
    else if (nWAIT)
      begin
        if (~ex_enbar)
          inst_type_ex <= inst_type_in;  
      end
  end

//This block controls the 's' latch
//synopsys async_set_reset "nRESET"
always @(posedge nGCLK or negedge nRESET)
  begin   
    if (!nRESET)
      s <= 1'b0;
    else if (nWAIT)
      begin
        if (~ex_enbar)
          s <= s_id;
      end
  end

//This block controls the mul_first_ex latch
//synopsys async_set_reset "nRESET"
always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      mul_first_ex <= 1'b0;
    else if (nWAIT)
      begin
        if (~ex_enbar)
          mul_first_ex <= mul_first_id;
      end
  end

//This block controls the mul_first_ex latch
//synopsys async_set_reset "nRESET"
always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      double_ex <= 1'b0;
    else if (nWAIT)
      begin
        if (~ex_enbar)
          double_ex <= double_id;
      end
  end

//This block controls the 'ir_id' register
//synopsys async_set_reset "nRESET"
always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      ir_ex[6:4] <= 3'b000;
    else if (nWAIT)
      begin
        if (~ex_enbar)
          ir_ex[6:4] <= ir_id[6:4];
      end
  end

//This block controls the cop_mem_ex register
//synopsys async_set_reset "nRESET"
always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      cop_mem_ex <= 1'b0;
    else if (nWAIT)
      begin
        if (~ex_enbar)
          cop_mem_ex <= cop_mem_id;   
      end
  end

//This block controls the CPSR register
always @(posedge nGCLK)
  begin
    if (nWAIT)
      begin
        if (~cpsr_disable)
          CPSR <= next_cpsr;
      end
  end

//Create the SPSR's
wire spsr_fiq_disable = ~((write_spsr_index == 3'h0) && 
			  ((!ex_enbar & !was_disabled) | exception_ex));
always @(posedge nGCLK)
  begin
    if (nWAIT)
      begin
	if (~spsr_fiq_disable)
	  spsr_fiq <= next_spsr;
      end
  end

wire spsr_svc_disable = ~(((write_spsr_index == 3'h1) && ((!ex_enbar
                && !was_disabled) | exception_ex)) || (!nRESET));
always @(posedge nGCLK)
  begin
    if (nWAIT)
      begin
        if (~spsr_svc_disable)
          spsr_svc <= next_spsr;
      end
  end

wire spsr_abt_disable = ~((write_spsr_index == 3'h2) && 
			  ((!ex_enbar & !was_disabled) | exception_ex));

always @(posedge nGCLK)
  begin
    if (nWAIT)
      begin
        if (~spsr_abt_disable)
          spsr_abt <= next_spsr;
      end
  end

wire spsr_irq_disable = ~((write_spsr_index == 3'h3) && 
			  ((!ex_enbar & !was_disabled) | exception_ex));

always @(posedge nGCLK)
  begin
    if (nWAIT)
      begin
        if (~spsr_irq_disable)
          spsr_irq <= next_spsr;
      end
  end

wire spsr_und_disable = ~((write_spsr_index == 3'h4) &&
			  ((!ex_enbar & !was_disabled) | exception_ex));

always @(posedge nGCLK)
  begin
    if (nWAIT)
      begin
        if (~spsr_und_disable)
            spsr_und <= next_spsr;
      end
  end

//This block captures the nRESET so that some events
//only occur once during the reset cycle (i.e. spsr_svc = CPSR)
//synopsys async_set_reset "nRESET"
always @(posedge nGCLK or posedge nRESET)
    begin
	if (nRESET)
	    latched_nRESET <= 1'b1;
	else if (nWAIT)
	    latched_nRESET <= nRESET;
    end

//This block is a memory of the last two instructions
//and their effect on the pc
//synopsys async_set_reset "nRESET"
always @(posedge nGCLK or negedge nRESET)
    begin
	if (~nRESET)
	    me_mod_pc <= 1'b0;
	else if (nWAIT)
	    me_mod_pc <= ex_mod_pc;
    end

//This block monitors the cop_mem_ex signal
//synopsys async_set_reset "nRESET"
always @(posedge nGCLK or negedge nRESET)
    begin
        if (~nRESET)
	    ldc_stc <= 1'b0;
	else if (nWAIT)
	    ldc_stc <= cop_mem_ex & ex_enbar;
    end

//This block controls the PASS signal.  It is triggered
//during the 2nd phase of the clock (when its high)
//synopsys async_set_reset "nRESET"
always @(negedge nGCLK or negedge nRESET)
    begin
	if (~nRESET)
	    PASS <= 1'b0;
	else if (nWAIT)
	    PASS <= (cdp | mrcmcr) & !cond_failed_ex & 
			!me_mod_pc;
    end

//This ff latches the take exception signal
//synopsys async_set_reset "nRESET"
always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      exception_ex <= 1'b0;
    else if (nWAIT)
      begin
        if (~ex_enbar)
          exception_ex <= exception;
      end
  end

//These 2 ff's latch the exception code
//synopsys async_set_reset "nRESET"
always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      exc_code_ex <= 2'h0;
    else if (nWAIT)
      begin
	if (~ex_enbar)
	  exc_code_ex <= exc_code;
      end
  end

//This just latches the Stop Signal
//synopsys async_set_reset "nRESET"
always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      stop_ex <= 1'b0;
    else if (nWAIT)
      begin
        if (~ex_enbar)
          stop_ex <= stop_id;
      end
  end

endmodule