ex.v

arm9_fpga2_verilog是一个可以综合的用verilog写的arm9的ip软核

`timescale 1ns/10ps
`include "pardef"
/*****************************************************************************
$RCSfile: ex.v,v $
$Revision: 1.6 $
$Author: kohlere $
$Date: 2000/04/17 18:12:48 $
$State: Exp $
$Source: /home/lefurgy/tmp/ISC-repository/isc/hardware/ARM10/behavioral/pipelined/fpga2/ex.v,v $

Description:  This is the Execution Stage of the Pipeline.  It 
		contains the Shifter, ALU, and PSR's.  

Note:	In the earlier versions, I saved the RF address decode until the
	registers were accessed.  This was going to cause problems for
	instructions that had different modes when it came to writing and
	forwarding data.  Now that I decode the address in the ID stage, 
	any place where I was using Rn[0] as a bit of the instruction is
	wrong. However, due to the fortunate nature of my coding scheme,
	any register with and even address will always map to an even
	addressed register and vice versa, so the decoded register address
	bit 0 will be equal to the intruction register address bit 0.

*****************************************************************************/

module ex(nGCLK, nWAIT, nRESET, ex_enbar, op1_in, op2_in,
		alu_opcode_in, addr_me, condition_in, shift_amount_in,
		shift_type_in, ir_id, Rd_id, Rn_id, id_second,
		need_2cycles_id, inst_type_in, s_id, ex_result,
 		store_addr, Rd_ex, Rn_ex, second_ex,
		inst_type_ex, mode, signed_byte_ex, write_Rd_ex,
		write_Rn_ex, unsigned_byte_ex, aux_data_id, 
		unsigned_hw_ex, signed_hw_ex, base_ex, mul_first_id,
		double_id, double_ex, double_me, cpsr_flags, load_use_id,
		cop_mem_id, pc_mod_ex, hold_next_ex, mcr_ex, cop_mem_ld,
		store_ex, mispredicted, exc_code, load_pc_ex, cop_mem_st,
		fiq_disable, irq_disable, exception, write_Pc_Rn, 
		write_Pc_Rd, DnMREQ, PASS, DnWR, stop_id, stop_ex);

/*------------------------------------------------------------------------
        Ports
------------------------------------------------------------------------*/

input	[31:0] 	op1_in;			//OP1 from ID stage
input	[31:0] 	op2_in;			//OP2 from ID stage
input	[31:0] 	aux_data_id;		//Auxillary Data from ID stage
input	[31:0] 	addr_me;		//Address from ME stage
input	[7:0]  	shift_amount_in;	//Shift by this amount
input	[4:0]  	Rd_id;			//First(Main) Destination Register
input	[4:0]  	Rn_id;			//Second Destination Register
input	[3:0]  	alu_opcode_in;		//Alu Opcode
input	[3:0]  	condition_in;		//Condition of Execution
input	[3:0]  	inst_type_in;		//Instruction Code
input	[2:0]  	shift_type_in;		//Shift Controls
input	[6:4]  	ir_id;			//Bits 6-5 of Ir
input	[1:0]	exc_code;		//Which Exception
input		nGCLK;			//clock signal
input		nWAIT;			//clock enable
input		nRESET;			//reset signal
input		exception;		//Take Exception
input		ex_enbar;		//EX stage enable (active low)
input		id_second;		//ID Stage in Second Cycle
input		need_2cycles_id;	//Need_2cycles For this instruction
input		load_use_id;		//Need_2cycles due to Load Use
input		s_id;			//S Bit of Instruction
input		mul_first_id;		//First Cycle of LDM/STM
input		double_id;		//64-bit Memory Access
input		double_me;		//Inc by 4 or 8?
input		cop_mem_id;		//Coprocessor requiring Memory
input		mispredicted;		//Mispredicted Branch
input		stop_id;		//Stop Execution

output 	[31:0] 	ex_result;		//Result of Execution
output 	[31:0] 	store_addr;		//Usually Address
output 	[31:0] 	base_ex;		//Base Address
output 	[4:0]  	mode;			//Current Processor Mode
output 	[4:0]  	Rd_ex;			//Latched Fisrt Destination Reg
output 	[4:0]  	Rn_ex;			//Latched Second Destination Reg
output 	[3:0]  	cpsr_flags;		//Flags from CPSR
output 	[3:0]  	inst_type_ex;		//Instruction Code
output		write_Pc_Rd;		//Inst May Write PC in Rd field
output		write_Pc_Rn;		//Inst May Write PC in Rn field
output		fiq_disable;		//FIQ's Disabled (CPSR[6])
output		irq_disable;		//IRQ's Disabled (CPSR[6])
output	      	second_ex;		//Second Cycle of Instruction
output		store_ex;		//Inst should Store in ME cycle
output		write_Rn_ex;		//Write Back Signal
output		write_Rd_ex;		//Write to Destination?
output		unsigned_byte_ex;	//Inst uses Unsigned bytes
output		signed_byte_ex;		//Inst uses Signed Bytes
output		unsigned_hw_ex;		//Inst uses Unsigned Halfwords  
output		signed_hw_ex;		//Inst uses Signed Halfwords
output		double_ex;		//64-bit Memory Access
output		pc_mod_ex;		//One of last two inst modified pc
output		load_pc_ex;		//Load to the PC
output		hold_next_ex;		//Ex Stage requires another cycle
output		mcr_ex;			//Ex Stage has MCR
output		cop_mem_ld;		//Coprocessor Performing a Load
output		cop_mem_st;		//Coprocessor Performing a Store
output		PASS;			//Coprocessor should execute
output		DnMREQ;			//Data Not Memory Request
output		DnWR;			//Data Not Write Read
output		stop_ex;		//Stop Execution

/*------------------------------------------------------------------------
        Variable Declarations
------------------------------------------------------------------------*/

//Declare Outputs of Combinational Logic
wire	[63:0]	mult_result;		//Output from Multiplier
wire    [63:0]  acc_op1;                //Mult Op1 to Add
wire    [63:0]  acc_op2;                //Mult Op2 to Add
wire    [63:0]  alu_op1;                //Op1 to ALU
wire    [63:0]  alu_op2;                //Op2 to ALU
wire	[31:0]	upper_mult;		//Output from Upper Adder
wire	[31:0]	alu_result;		//Output from ALU
wire	[31:0]	shifted_op2;		//Output from Shifter
wire	[31:0]	inc_add;		//Incremented Address
wire	[4:0]	mode;			//Processor Mode
wire	[3:0]	cpsr_flags;		//CPSR[31:28]
wire	[3:0]	alu_flags;		//Flags from ALU 
wire	[2:0]	spsr_index;		//SPSR Index
wire	[1:0]	mult_flags;		//Mult Flags (N,Z)
wire		fiq_disable;		//CPSR[6]
wire		irq_disable;		//CPSR[7]
wire		store_ex;		//Want to Store On next Cycle
wire		signed_byte_ex;		//Inst uses Signed Bytes
wire		unsigned_byte_ex;	//Inst uses Unsigned Bytes
wire		signed_hw_ex;		//Inst uses Signed Halfwords
wire		unsigned_hw_ex;		//Inst uses Unsigned Halfwords
wire		shift_c_out;		//Shifter Carry Output
wire		multiply;		//MUL/MULL inst
wire		mult_res;		//Multiplier Reset
wire		cop_mem_ld;		//Coprocessor going to Load
wire		cop_mem_st;		//Coprocessor going to Stall
wire		inst_exception;		//SWI or UND
wire		alu;			//ALU inst
wire		str;			//STRW/STRH inst
wire		ldr;			//LDRW/LDRH inst
wire		branch;			//BR/BL inst
wire		swap;			//Swap inst
wire		mrs;			//MRS inst
wire		und;			//Undefined Inst
wire		swi;			//SWI Inst
wire		msr;			//MSR inst
wire		mrc;			//MRC inst
wire		mcr_ex;			//MCR inst
wire		ldm;			//LDM inst
wire		stm;			//STM inst
wire		load;			//Inst is a Load
wire		load_pc_ex;		//Inst is a Load to the PC
wire		N;			//N Flag from CPSR
wire		Z;			//Z Flag from CPSR
wire		C;			//C Flag from CPSR
wire		V;			//V Flag from CPSR
wire		write_Rn_ex;		//Write Back Base?
wire		u;			//Inc/Dec
wire		write_Rd_ex;		//Write to Rd?
wire		write_Pc_Rn;		//Write to PC (Rn)
wire		write_Pc_Rd;		//Write to PC (Rd)
wire		r15_inlist;		//R15 in Transfer List
wire		rd_pc;			//Rd is the PC
wire		alu_no_wb;		//Alu Inst with No WB
wire		no_writes;		//No Write Back this Cycle
wire		link;			//Link on Branches?
wire		long;			//Long Multiply Required
wire		acc;			//Accumulate
wire		cdp;			//Coprocessor Data Operation
wire		mrcmcr;			//Coprocessor Register Transfer
wire		pc_mod_ex;		//One of Last 2 inst modified pc
wire		hold_next_ex;		//Disable Registers for Next Cycle
wire		ex_mod_pc;		//PC will be modified
wire		cpsr_disable;		//Write to CPSR?
wire		DnMREQ;			//Data Access next Cycle
wire		DnWR;			//Data Not Write Read

//Declare Outputs of Multiplexers and Registers
reg	[31:0]	ex_result;		//Final Muxed Result
reg	[31:0]	store_addr;		//Address to be stored/loaded
reg	[31:0]	aux_data_ex;		//Auxillary Data 
reg	[31:0]	CPSR;			//Current Program Status Reg.
reg	[31:0]	spsr_fiq;		//Saved Program Status Register
reg	[31:0]	spsr_svc;		//Saved Program Status Register
reg	[31:0]	spsr_abt;		//Saved Program Status Register
reg	[31:0]	spsr_irq;		//Saved Program Status Register
reg	[31:0]	spsr_und;		//Saved Program Status Register
reg	[31:0]	op1;			//First Operand Register
reg	[31:0]	op2;			//Second Operand Register
reg	[31:0]	psr;			//CPSR/SPSR for MRS Instructions
reg	[31:0]	next_cpsr;		//Next Value to load into CPSR
reg	[31:0]	next_spsr;		//Next Value to load into SPSR
reg	[31:0]	flg_all_spsr;		//Muxed value from Shifted_Op2
reg	[31:0]	current_spsr;		//Current SPSR
reg	[31:0]	base_ex;		//Base Value for Post-Indexed
reg	[31:0]	cpsr_const;		//Possible Next CPSR Constant Value
reg	[7:0]	increment;		//4/8 for LDM/STM's
reg	[31:0]	addr_2b_inc;		//Input Address to Incrementer
reg	[7:0]	shift_amount;		//Shift Amount Register 
reg	[4:0]	Rd_ex;			//First Destination Reg
reg	[4:0]	Rn_ex;			//Second Destination Reg
reg	[3:0]	inst_type_ex;		//Latched Instr. Code
reg	[3:0]	condition;		//Condition of Execution
reg	[3:0]	alu_opcode;		//Opcode from ID Stage
reg	[3:0]	opcode;			//Multiplexed Opcode (LD/ST)
reg	[3:0]	flags_from_alu;		//Flags From ALU/SHIFTER
reg	[3:0]	early_flags;		//Flags Available Early
reg	[2:0]	shift_type;		//Shift Control Register
reg	[2:0]	write_spsr_index;	//Indicates which SPSR to update
reg	[6:4]	ir_ex;			//IR bits 6-5
reg	[1:0]	exc_code_ex;		//Exception Code
reg		exception_ex;		//Exception
reg		was_disabled;		//Last Inst was squashed
reg		second_ex;		//Second Cycle of Instruction
reg		need_2cycles_ex;	//Need 2 cycles for Current inst
reg		load_use_ex;		//Need 2 cycles due to Load Use
reg		cond_failed_ex;		//Inst Does Not Meet Condition
reg		s;			//S-Bit of Instruction
reg		stop_ex;		//Stop Execution
reg		mul_first_ex;		//First Cycle of LDM/STM
reg		double_ex;		//64-bit Memory Access
reg		latched_nRESET;		//One cycle delayed
reg		cop_mem_ex;		//Cop. Inst requiring Memory
reg		me_mod_pc;		//PC to be modified by inst in ME
reg		ldc_stc;		//LDC/STC inst
reg		PASS;			//Cop. should Execute Inst.

/*------------------------------------------------------------------------
        Basic Assignments
------------------------------------------------------------------------*/

//Detect several types of instructions
assign swap 	= (inst_type_ex == `SWAP);
assign multiply = ((inst_type_ex == `MUL) || (inst_type_ex == `MULL));
assign mult_res = (cond_failed_ex | me_mod_pc | was_disabled 
			| load_use_ex | mispredicted | !nRESET);
assign alu_op1	= (multiply) ? acc_op1 : {32'h00000000,op1};
assign alu_op2 	= (multiply) ? acc_op2 : {32'h00000000,shifted_op2};
assign alu 	= (inst_type_ex == `ALU);
assign str 	= ((inst_type_ex == `STRW) || (inst_type_ex == `STRH));
assign ldr 	= ((inst_type_ex == `LDRW) || (inst_type_ex == `LDRH));
assign branch 	= (inst_type_ex == `BR);
assign mrs 	= (inst_type_ex == `MRS);
assign msr 	= (inst_type_ex == `MSR);
assign link 	= alu_opcode[3];
assign long 	= (inst_type_ex == `MULL);
assign ldm 	= (inst_type_ex == `LDM);
assign stm 	= (inst_type_ex == `STM);
assign acc 	= (alu_opcode[0]);
assign und	= (inst_type_ex == `UND);
assign swi	= (inst_type_ex == `SWI);
assign fiq_disable	= CPSR[6];
assign irq_disable	= CPSR[7];
assign cop_mem_ld	= cop_mem_ex & s;
assign cop_mem_st	= cop_mem_ex & ~s & ~alu_opcode[1];
assign inst_exception 	= und | swi;
assign mult_result 	= {upper_mult,alu_result};
assign pc_mod_ex	= me_mod_pc | 
			  (write_Pc_Rn && (Rn_ex == 5'h0F)) | 
			  (write_Pc_Rd && (Rd_ex == 5'h0F));
assign #1 cpsr_flags 	= CPSR[31:28];
assign N 		= CPSR[31];
assign Z 		= CPSR[30];
assign C 		= CPSR[29];
assign V 		= CPSR[28];
assign mult_flags[1] 	= (long) ? mult_result[63] : mult_result[31];
assign mult_flags[0]	= (long) ? (~(| mult_result[63:32]) & alu_flags[2])
				 : alu_flags[2];

//This will detect the CDP Instruction
assign cdp = ((inst_type_ex == `COP) && (!ir_ex[4]));

//This will detect an MRC or MCR
assign mrcmcr = ((inst_type_ex == `COP) && (ir_ex[4]));

//This will determine the MRC
assign mrc = mrcmcr & s;

//This will determine the MCR
assign mcr_ex = mrcmcr & ~s;

//This is the address incrementer...its a 32'bit adder.  Maybe better
//if the increment is just 4 bits?
assign inc_add = addr_2b_inc + {{24{increment[7]}},increment};

//The TEQ, TST, CMN, and CMP Instructions do not write back
//the results of the instruction to Rd
assign alu_no_wb = ((opcode == `TEQ) || (opcode == `TST) ||
		    (opcode == `CMN) || (opcode == `CMP));

//There is usually no need to write to Rd on the 1st
//Cycle of instructions requiring two cycles.
assign no_writes = (need_2cycles_ex & !second_ex & !swap) | (load_use_ex);

//Write the Base Back on Long Multiplies (mult_res[63:32) and 
//any ldr/str with write back bit set.  WB is implied on ldr/str with
//post index addressing.  Also write back the base (R14)
//on BL instructions.  No writeback for non-executed instructions.
//Also write back for LDC/STC with W-Bit set
// write_Rn_ex = (fail)' . (bl + (cop_mem_ex . w) + ((ldm + stm).mul_first) 
//			+ (ldm.double) + und + 
//		(nw' . (MULL + ((ldr + str).ao[0]))))
 
//Might not need to base writeback in exceptions *******
assign write_Rn_ex = exception_ex |
	(!cond_failed_ex & !was_disabled & !hold_next_ex &
	((branch & link) | (und) | (swi) | 
	(cop_mem_ex & alu_opcode[0]) | (ldm & double_ex) |
	(mul_first_ex & alu_opcode[0]) |
	(!no_writes & 
		((long) | 
		((ldr | str) & (alu_opcode[0] | !alu_opcode[3]))))));

//Write to PC where Rn = PC
//Ignore from multiplies, mrc (only updates flags), mrs, swap, bl, und, 
//swi, ldr, cop_mem (ldc, stc) 
//For above instruction, Rn should never be R15 (PC)
//This is only a signal that indicates that PC may be written,
//Rn must still be compared to PC
assign write_Pc_Rn = !cond_failed_ex & !was_disabled & (ldm & double_ex);

//Write to Rd if the condition passes and there is a branch, or
//on the 1st cycle of a swap or on the final cycle of a  
//mul/ldr/alu (wb specified) or on a mrc
//write_Rd_ex=(fail)'.(branch + und + mrc + mrs + ldm + (swap.sec')+
//		(nw'.(mul+ldr+(ALU.nowb'))))

assign write_Rd_ex = 
	(!cond_failed_ex & !was_disabled & !no_writes & !hold_next_ex &
		!exception_ex & (branch | mrc | mrs | ldm | und | 
		(swap & !second_ex) | multiply | ldr | swi | 
		(alu & !alu_no_wb)));

//Write to PC where Rd = Pc
//Ignore from multiplies, mrc (only updates flags), mrs, swap
//For above instruction, Rd should never be R15 (PC)
//This is only a signal that indicates that PC may be written,
//Rd must still be compared to PC
assign #1 write_Pc_Rd = !cond_failed_ex & !was_disabled & !no_writes 
			& !exception_ex & 
		(branch | ldm | und | ldr | swi | (alu & !alu_no_wb));

//Assign the Unsigned Bit for Long Multiplication
assign u = alu_opcode[2];

//Instructions using Unsigned Bytes are STRB, LDRB, SWPB
assign unsigned_byte_ex = (((inst_type_ex == `STRW)||
                            (inst_type_ex == `LDRW)||
                            (inst_type_ex == `SWAP)) &&
                            (alu_opcode[1]));

//Instructions using Signed Bytes are LDRSB
assign signed_byte_ex = ((inst_type_ex == `LDRH) && (ir_ex[6:5] == 2'b10));

//Instructions using Unsigned Halfwords are STRH, LDRH
assign unsigned_hw_ex = (((inst_type_ex == `STRH) ||
                          (inst_type_ex == `LDRH)) &&
                          (ir_ex[6:5] == 2'b01));

//Instructions using Signed Halfwords are LDRSH
assign signed_hw_ex = ((inst_type_ex == `LDRH) && (ir_ex[6:5] == 2'b11));

//Determine whether this instruction will modify the PC
assign ex_mod_pc = (((Rd_ex == 5'h0F) & write_Rd_ex) |
                    ((Rn_ex == 5'h0F) & write_Rn_ex)) & !me_mod_pc;

//Determine whether or not CPSR can be updated
assign cpsr_disable = ~((!was_disabled & !me_mod_pc & !load_use_ex &
		         !mispredicted & !cond_failed_ex & 
                         !(need_2cycles_ex & !second_ex)) | 
		         (!nRESET | exception_ex));

//this tells ME to drive the DD Bus
assign store_ex = (((str & !id_second) | 
		    (stm) |
		    (swap & second_ex)) & !load_use_ex &
			!cond_failed_ex & !me_mod_pc & !was_disabled);

//This tells the cache its a store/read
assign DnWR = ~(((str & !id_second) |
                    (stm) |
                    (swap & second_ex)
                    | (cop_mem_st)) & !load_use_ex &
                        !cond_failed_ex & !me_mod_pc & !was_disabled);

assign r15_inlist = ((Rd_ex == 5'h0F) | (Rn_ex == 5'h0F));
assign rd_pc	= (Rd_ex == 5'h0F);

assign load = ((inst_type_ex == `LDRW)||
               (inst_type_ex == `LDRH)||