xilinx_pkg.vhd

arm9_fpga2_verilog是一个可以综合的用verilog写的arm9的ip软核

  attribute syn_noprune  of OBUF_SSTL2_II : component is TRUE;
  attribute black_box of OBUF_SSTL2_II : component is true;
  attribute black_box_pad_pin of OBUF_SSTL2_II : component is "O";

  component OBUF_SSTL3_I
    port
    (
      I : in std_logic;
      O : out std_logic
    );
  end component;
  attribute syn_noprune  of OBUF_SSTL3_I : component is TRUE;
  attribute black_box of OBUF_SSTL3_I : component is true;
  attribute black_box_pad_pin of OBUF_SSTL3_I : component is "O";

  component OBUF_SSTL3_II
    port
    (
      I : in std_logic;
      O : out std_logic
    );
  end component;
  attribute syn_noprune  of OBUF_SSTL3_II : component is TRUE;
  attribute black_box of OBUF_SSTL3_II : component is true;
  attribute black_box_pad_pin of OBUF_SSTL3_II : component is "O";

  component OBUF_F_24
    port
    (
      I : in std_logic;
      O : out std_logic
    );
  end component;
  attribute syn_noprune  of OBUF_F_24 : component is TRUE;
  attribute black_box of OBUF_F_24 : component is true;
  attribute black_box_pad_pin of OBUF_F_24 : component is "O";

  component OBUF_S_24
    port
    (
      I : in std_logic;
      O : out std_logic
    );
  end component;
  attribute syn_noprune  of OBUF_S_24 : component is TRUE;
  attribute black_box of OBUF_S_24 : component is true;
  attribute black_box_pad_pin of OBUF_S_24 : component is "O";

  component OBUF_F_12
    port
    (
      I : in std_logic;
      O : out std_logic
    );
  end component;
  attribute syn_noprune  of OBUF_F_12 : component is TRUE;
  attribute black_box of OBUF_F_12 : component is true;
  attribute black_box_pad_pin of OBUF_F_12 : component is "O";

  component OBUF_S_12
    port
    (
      I : in std_logic;
      O : out std_logic
    );
  end component;
  attribute syn_noprune  of OBUF_S_12 : component is TRUE;
  attribute black_box of OBUF_S_12 : component is true;
  attribute black_box_pad_pin of OBUF_S_12 : component is "O";

  component OBUF_F_8
    port
    (
      I : in std_logic;
      O : out std_logic
    );
  end component;
  attribute syn_noprune  of OBUF_F_8 : component is TRUE;
  attribute black_box of OBUF_F_8 : component is true;
  attribute black_box_pad_pin of OBUF_F_8 : component is "O";

  component OBUF_S_8
    port
    (
      I : in std_logic;
      O : out std_logic
    );
  end component;
  attribute syn_noprune  of OBUF_S_8 : component is TRUE;
  attribute black_box of OBUF_S_8 : component is true;
  attribute black_box_pad_pin of OBUF_S_8 : component is "O";

  component OBUFT
    port
    (
      T : in std_logic;
      I : in std_logic;
      O : out std_logic
    );
  end component;
  attribute syn_noprune  of OBUFT : component is TRUE;
  attribute black_box of OBUFT : component is true;
  attribute black_box_pad_pin of OBUFT : component is "O";
  attribute black_box_tri_pins of OBUFT : component is "O";

  component OBUFT_SSTL2_I
    port
    (
      T : in std_logic;
      I : in std_logic;
      O : out std_logic
    );
  end component;
  attribute syn_noprune  of OBUFT_SSTL2_I : component is TRUE;
  attribute black_box of OBUFT_SSTL2_I : component is true;
  attribute black_box_pad_pin of OBUFT_SSTL2_I : component is "O";
  attribute black_box_tri_pins of OBUFT_SSTL2_I : component is "O";

  component OBUFT_SSTL2_II
    port
    (
      T : in std_logic;
      I : in std_logic;
      O : out std_logic
    );
  end component;
  attribute syn_noprune  of OBUFT_SSTL2_II : component is TRUE;
  attribute black_box of OBUFT_SSTL2_II : component is true;
  attribute black_box_pad_pin of OBUFT_SSTL2_II : component is "O";
  attribute black_box_tri_pins of OBUFT_SSTL2_II : component is "O";

  component OBUFT_SSTL3_I
    port
    (
      T : in std_logic;
      I : in std_logic;
      O : out std_logic
    );
  end component;
  attribute syn_noprune  of OBUFT_SSTL3_I : component is TRUE;
  attribute black_box of OBUFT_SSTL3_I : component is true;
  attribute black_box_pad_pin of OBUFT_SSTL3_I : component is "O";
  attribute black_box_tri_pins of OBUFT_SSTL3_I : component is "O";

  component OBUFT_SSTL3_II
    port
    (
      T : in std_logic;
      I : in std_logic;
      O : out std_logic
    );
  end component;
  attribute syn_noprune  of OBUFT_SSTL3_II : component is TRUE;
  attribute black_box of OBUFT_SSTL3_II : component is true;
  attribute black_box_pad_pin of OBUFT_SSTL3_II : component is "O";
  attribute black_box_tri_pins of OBUFT_SSTL3_II : component is "O";

  component OBUFT_F_24
    port
    (
      T : in std_logic;
      I : in std_logic;
      O : out std_logic
    );
  end component;
  attribute syn_noprune  of OBUFT_F_24 : component is TRUE;
  attribute black_box of OBUFT_F_24 : component is true;
  attribute black_box_pad_pin of OBUFT_F_24 : component is "O";
  attribute black_box_tri_pins of OBUFT_F_24 : component is "O";

  component OBUFT_S_24
    port
    (
      T : in std_logic;
      I : in std_logic;
      O : out std_logic
    );
  end component;
  attribute syn_noprune  of OBUFT_S_24 : component is TRUE;
  attribute black_box of OBUFT_S_24 : component is true;
  attribute black_box_pad_pin of OBUFT_S_24 : component is "O";
  attribute black_box_tri_pins of OBUFT_S_24 : component is "O";

  component OBUFT_F_12
    port
    (
      T : in std_logic;
      I : in std_logic;
      O : out std_logic
    );
  end component;
  attribute syn_noprune  of OBUFT_F_12 : component is TRUE;
  attribute black_box of OBUFT_F_12 : component is true;
  attribute black_box_pad_pin of OBUFT_F_12 : component is "O";
  attribute black_box_tri_pins of OBUFT_F_12 : component is "O";

  component OBUFT_S_12
    port
    (
      T : in std_logic;
      I : in std_logic;
      O : out std_logic
    );
  end component;
  attribute syn_noprune  of OBUFT_S_12 : component is TRUE;
  attribute black_box of OBUFT_S_12 : component is true;
  attribute black_box_pad_pin of OBUFT_S_12 : component is "O";
  attribute black_box_tri_pins of OBUFT_S_12 : component is "O";

  component OBUFT_F_8
    port
    (
      T : in std_logic;
      I : in std_logic;
      O : out std_logic
    );
  end component;
  attribute syn_noprune  of OBUFT_F_8 : component is TRUE;
  attribute black_box of OBUFT_F_8 : component is true;
  attribute black_box_pad_pin of OBUFT_F_8 : component is "O";
  attribute black_box_tri_pins of OBUFT_F_8 : component is "O";

  component OBUFT_S_8
    port
    (
      T : in std_logic;
      I : in std_logic;
      O : out std_logic
    );
  end component;
  attribute syn_noprune  of OBUFT_S_8 : component is TRUE;
  attribute black_box of OBUFT_S_8 : component is true;
  attribute black_box_pad_pin of OBUFT_S_8 : component is "O";
  attribute black_box_tri_pins of OBUFT_S_8 : component is "O";

  component One_Shot
    port
    (
      Clk  : in std_logic;
      I   : in std_logic;
      O : out std_logic
    );
  end component;
  attribute black_box of One_Shot : component is true;

  component PULLDOWN
    port ( O : out std_logic );
  end component;
  attribute black_box of PULLDOWN : component is true;
  attribute black_box_pad_pin of PULLDOWN : component is "O";

  component PULLUP
    port ( O : out std_logic );
  end component;
  attribute black_box of PULLUP : component is true;
  attribute black_box_pad_pin of PULLUP : component is "O";

  component RAM32X1S
    port
    (
      O    : out std_logic;
      A0   : in std_logic;
      A1   : in std_logic;
      A2   : in std_logic;
      A3   : in std_logic;
      A4   : in std_logic;
      D    : in std_logic;
      WCLK : in std_logic;
      WE   : in std_logic
    );
  end component;
  attribute black_box of RAM32X1S : component is true;

  component RAMB_256x32_DP is
-- synopsys synthesis_off
---    generic
---    (
---      INIT_FILE_NAME : string := "RAMB_256x32_DP.mif"
---    );
-- synopsys synthesis_on
    port
    (
      addra : in    std_logic_vector(7 DOWNTO 0);
      addrb : in    std_logic_vector(7 DOWNTO 0);
      dia   : in    std_logic_vector(31 DOWNTO 0);
      dib   : in    std_logic_vector(31 DOWNTO 0);
      clka  : in    std_logic;
      clkb  : in    std_logic;
      wea   : in    std_logic;
      web   : in    std_logic;
      ena   : in    std_logic;
      enb   : in    std_logic;
      rsta  : in    std_logic;
      rstb  : in    std_logic;
      doa   :   out std_logic_vector(31 DOWNTO 0);
      dob   :   out std_logic_vector(31 DOWNTO 0)
    );
  end component;
  attribute black_box of RAMB_256x32_DP : component is true;
  
  component RAMB_256x16_DP is
-- synopsys synthesis_off
---    generic
---    (
---      INIT_FILE_NAME : string := "RAMB_256x16_DP.mif"
---    );
-- synopsys synthesis_on
    port
    (
      addra : in    std_logic_vector(7 DOWNTO 0);
      addrb : in    std_logic_vector(7 DOWNTO 0);
      dia   : in    std_logic_vector(15 DOWNTO 0);
      dib   : in    std_logic_vector(15 DOWNTO 0);
      clka  : in    std_logic;
      clkb  : in    std_logic;
      wea   : in    std_logic;
      web   : in    std_logic;
      ena   : in    std_logic;
      enb   : in    std_logic;
      rsta  : in    std_logic;
      rstb  : in    std_logic;
      doa   :   out std_logic_vector(15 DOWNTO 0);
      dob   :   out std_logic_vector(15 DOWNTO 0)
    );
  end component;
  attribute black_box of RAMB_256x16_DP : component is true;

  component STARTUP
    port (
      GSR : in std_logic;
      GTS : in std_logic;
      CLK : in std_logic
    );
  end component;
  attribute syn_noprune of STARTUP : component is true;
  attribute black_box of STARTUP : component is true;

  component STARTUP_VIRTEX
    port
    (
      GSR : in std_logic;
      GTS : in std_logic;
      CLK : in std_logic
    );
  end component;
  attribute syn_noprune of STARTUP_VIRTEX : component is true;
  attribute black_box of STARTUP_VIRTEX : component is true;

  component STARTUP_VIRTEX_ALL
    port
    (
      GSR : in std_logic;
      GTS : in std_logic;
      CLK : in std_logic
    );
  end component;
  attribute syn_noprune of STARTUP_VIRTEX_ALL : component is true;
  attribute black_box of STARTUP_VIRTEX_ALL : component is true;
  attribute xc_alias of STARTUP_VIRTEX_ALL: component is "STARTUP_VIRTEX";

  component STARTUP_VIRTEX_GTS
    port
    (
      GTS : in std_logic
    );
  end component;
  attribute syn_noprune of STARTUP_VIRTEX_GTS : component is true;
  attribute black_box of STARTUP_VIRTEX_GTS : component is true;
  attribute xc_alias of STARTUP_VIRTEX_GTS: component is "STARTUP_VIRTEX";

  component STARTUP_VIRTEX_GSR
    port
    (
      GSR : in std_logic
    );
  end component;
  attribute syn_noprune of STARTUP_VIRTEX_GSR : component is true;
  attribute black_box of STARTUP_VIRTEX_GSR : component is true;
  attribute xc_alias of STARTUP_VIRTEX_GSR: component is "STARTUP_VIRTEX";

  component STARTUP_VIRTEX_CLK
    port
    (
      CLK : in std_logic
    );
  end component;
  attribute syn_noprune of STARTUP_VIRTEX_CLK : component is true;
  attribute black_box of STARTUP_VIRTEX_CLK : component is true;
  attribute xc_alias of STARTUP_VIRTEX_CLK: component is "STARTUP_VIRTEX";

end Xilinx_Package;