xilinx_pkg.vhd

arm9_fpga2_verilog是一个可以综合的用verilog写的arm9的ip软核

  end component;
  attribute black_box of FDRE : component is TRUE;

  component FDRE_1 is
    port
    (
      C   : in    std_logic;
      CE  : in    std_logic;
      R   : in    std_logic;
      D   : in    std_logic;
      Q   :   out std_logic
    );
  end component;
  attribute black_box of FDRE_1 : component is TRUE;

  component FDS is
    port
    (
      C   : in    std_logic;
      S   : in    std_logic;
      D   : in    std_logic;
      Q   :   out std_logic
    );
  end component;
  attribute black_box of FDS : component is TRUE;

  component FDS_1 is
    port
    (
      C   : in    std_logic;
      S   : in    std_logic;
      D   : in    std_logic;
      Q   :   out std_logic
    );
  end component;
  attribute black_box of FDS_1 : component is TRUE;

  component FDSE is
    port
    (
      C   : in    std_logic;
      CE  : in    std_logic;
      S   : in    std_logic;
      D   : in    std_logic;
      Q   :   out std_logic
    );
  end component;
  attribute black_box of FDSE : component is TRUE;

  component FDSE_1 is
    port
    (
      C   : in    std_logic;
      CE  : in    std_logic;
      S   : in    std_logic;
      D   : in    std_logic;
      Q   :   out std_logic
    );
  end component;
  attribute black_box of FDSE_1 : component is TRUE;

  component IBUF
    port
    (
      I : in std_logic;
      O : out std_logic
    );
  end component;
  attribute syn_noprune  of IBUF : component is TRUE;
  attribute black_box of IBUF : component is true;
  attribute black_box_pad_pin of IBUF : component is "I";

  component IBUF_SSTL2_I
    port
    (
      I : in std_logic;
      O : out std_logic
    );
  end component;
  attribute syn_noprune  of IBUF_SSTL2_I : component is TRUE;
  attribute black_box of IBUF_SSTL2_I : component is true;
  attribute black_box_pad_pin of IBUF_SSTL2_I : component is "I";

  component IBUF_SSTL2_II
    port
    (
      I : in std_logic;
      O : out std_logic
    );
  end component;
  attribute syn_noprune  of IBUF_SSTL2_II : component is TRUE;
  attribute black_box of IBUF_SSTL2_II : component is true;
  attribute black_box_pad_pin of IBUF_SSTL2_II : component is "I";

  component IBUF_SSTL3_I
    port
    (
      I : in std_logic;
      O : out std_logic
    );
  end component;
  attribute syn_noprune  of IBUF_SSTL3_I : component is TRUE;
  attribute black_box of IBUF_SSTL3_I : component is true;
  attribute black_box_pad_pin of IBUF_SSTL3_I : component is "I";

  component IBUF_SSTL3_II
    port
    (
      I : in std_logic;
      O : out std_logic
    );
  end component;
  attribute syn_noprune  of IBUF_SSTL3_II : component is TRUE;
  attribute black_box of IBUF_SSTL3_II : component is true;
  attribute black_box_pad_pin of IBUF_SSTL3_II : component is "I";

  component IBUFG
    port
    (
      I : in std_logic;
      O : out std_logic
    );
  end component;
  attribute syn_noprune  of IBUFG : component is TRUE;
  attribute black_box of IBUFG : component is true;
  attribute black_box_pad_pin of IBUFG : component is "I";

  component IBUFG_SSTL2_I
    port
    (
      I : in std_logic;
      O : out std_logic
    );
  end component;
  attribute syn_noprune  of IBUFG_SSTL2_I : component is TRUE;
  attribute black_box of IBUFG_SSTL2_I : component is true;
  attribute black_box_pad_pin of IBUFG_SSTL2_I : component is "I";

  component IBUFG_SSTL2_II
    port
    (
      I : in std_logic;
      O : out std_logic
    );
  end component;
  attribute syn_noprune  of IBUFG_SSTL2_II : component is TRUE;
  attribute black_box of IBUFG_SSTL2_II : component is true;
  attribute black_box_pad_pin of IBUFG_SSTL2_II : component is "I";

  component IBUFG_SSTL3_I
    port
    (
      I : in std_logic;
      O : out std_logic
    );
  end component;
  attribute syn_noprune  of IBUFG_SSTL3_I : component is TRUE;
  attribute black_box of IBUFG_SSTL3_I : component is true;
  attribute black_box_pad_pin of IBUFG_SSTL3_I : component is "I";

  component IBUFG_SSTL3_II
    port
    (
      I : in std_logic;
      O : out std_logic
    );
  end component;
  attribute syn_noprune  of IBUFG_SSTL3_II : component is TRUE;
  attribute black_box of IBUFG_SSTL3_II : component is true;
  attribute black_box_pad_pin of IBUFG_SSTL3_II : component is "I";

  component IOB_FDC is
    port
    (
      C   : in    std_logic;
      CLR : in    std_logic;
      D   : in    std_logic;
      Q   :   out std_logic
    );
  end component;
  attribute black_box of IOB_FDC : component is TRUE;

  component IOB_FDC_1 is
    port
    (
      C   : in    std_logic;
      CLR : in    std_logic;
      D   : in    std_logic;
      Q   :   out std_logic
    );
  end component;
  attribute black_box of IOB_FDC_1 : component is TRUE;

  component IOB_FDCE is
    port
    (
      C   : in    std_logic;
      CE  : in    std_logic;
      CLR : in    std_logic;
      D   : in    std_logic;
      Q   :   out std_logic
    );
  end component;
  attribute black_box of IOB_FDCE : component is TRUE;

  component IOB_FDCE_1 is
    port
    (
      C   : in    std_logic;
      CE  : in    std_logic;
      CLR : in    std_logic;
      D   : in    std_logic;
      Q   :   out std_logic
    );
  end component;
  attribute black_box of IOB_FDCE_1 : component is TRUE;

  component IOB_FDP is
    port
    (
      C   : in    std_logic;
      PRE : in    std_logic;
      D   : in    std_logic;
      Q   :   out std_logic
    );
  end component;
  attribute black_box of IOB_FDP : component is TRUE;

  component IOB_FDP_1 is
    port
    (
      C   : in    std_logic;
      PRE : in    std_logic;
      D   : in    std_logic;
      Q   :   out std_logic
    );
  end component;
  attribute black_box of IOB_FDP_1 : component is TRUE;

  component IOB_FDPE is
    port
    (
      C   : in    std_logic;
      CE  : in    std_logic;
      PRE : in    std_logic;
      D   : in    std_logic;
      Q   :   out std_logic
    );
  end component;
  attribute black_box of IOB_FDPE : component is TRUE;

  component IOB_FDPE_1 is
    port
    (
      C   : in    std_logic;
      CE  : in    std_logic;
      PRE : in    std_logic;
      D   : in    std_logic;
      Q   :   out std_logic
    );
  end component;
  attribute black_box of IOB_FDPE_1 : component is TRUE;

  component IOB_FDR is
    port
    (
      C   : in    std_logic;
      R   : in    std_logic;
      D   : in    std_logic;
      Q   :   out std_logic
    );
  end component;
  attribute black_box of IOB_FDR : component is TRUE;

  component IOB_FDR_1 is
    port
    (
      C   : in    std_logic;
      R   : in    std_logic;
      D   : in    std_logic;
      Q   :   out std_logic
    );
  end component;
  attribute black_box of IOB_FDR_1 : component is TRUE;

  component IOB_FDRE is
    port
    (
      C   : in    std_logic;
      CE  : in    std_logic;
      R   : in    std_logic;
      D   : in    std_logic;
      Q   :   out std_logic
    );
  end component;
  attribute black_box of IOB_FDRE : component is TRUE;

  component IOB_FDRE_1 is
    port
    (
      C   : in    std_logic;
      CE  : in    std_logic;
      R   : in    std_logic;
      D   : in    std_logic;
      Q   :   out std_logic
    );
  end component;
  attribute black_box of IOB_FDRE_1 : component is TRUE;

  component IOB_FDS is
    port
    (
      C   : in    std_logic;
      S   : in    std_logic;
      D   : in    std_logic;
      Q   :   out std_logic
    );
  end component;
  attribute black_box of IOB_FDS : component is TRUE;

  component IOB_FDS_1 is
    port
    (
      C   : in    std_logic;
      S   : in    std_logic;
      D   : in    std_logic;
      Q   :   out std_logic
    );
  end component;
  attribute black_box of IOB_FDS_1 : component is TRUE;

  component IOB_FDSE is
    port
    (
      C   : in    std_logic;
      CE  : in    std_logic;
      S   : in    std_logic;
      D   : in    std_logic;
      Q   :   out std_logic
    );
  end component;
  attribute black_box of IOB_FDSE : component is TRUE;

  component IOB_FDSE_1 is
    port
    (
      C   : in    std_logic;
      CE  : in    std_logic;
      S   : in    std_logic;
      D   : in    std_logic;
      Q   :   out std_logic
    );
  end component;
  attribute black_box of IOB_FDSE_1 : component is TRUE;

  component MUXCY_L
    port 
    (
      DI : in std_logic;
      CI : in std_logic;
      S  : in std_logic;
      LO : out std_logic
    );
  end component;
  attribute black_box of MUXCY_L : component is TRUE;

  component OBUF
    port
    (
      I : in std_logic;
      O : out std_logic
    );
  end component;
  attribute syn_noprune  of OBUF : component is TRUE;
  attribute black_box of OBUF : component is true;
  attribute black_box_pad_pin of OBUF : component is "O";

  component OBUF_SSTL2_I
    port
    (
      I : in std_logic;
      O : out std_logic
    );
  end component;
  attribute syn_noprune  of OBUF_SSTL2_I : component is TRUE;
  attribute black_box of OBUF_SSTL2_I : component is true;
  attribute black_box_pad_pin of OBUF_SSTL2_I : component is "O";

  component OBUF_SSTL2_II
    port
    (
      I : in std_logic;
      O : out std_logic
    );
  end component;