pe_pkg.vhd

arm9_fpga2_verilog是一个可以综合的用verilog写的arm9的ip软核

    );

  component Clock_Std_IF is
    generic
    (
      M_CLK_DLL_TYPE  : INTEGER := LOW_FREQ;
      P_CLK_DLL_TYPE  : INTEGER := LOW_FREQ;
      U_CLK_DLL_TYPE  : INTEGER := LOW_FREQ
    );
    port
    (
      Pads      : inout Clock_Pads_Type;
      User_In   :   out Clock_Std_IF_In_Type
    );
  end component;

  ----------------------------------------------------------------------
  --
  --  LAD_Bus_Std_IF_Type
  --
  --  Name Key:
  --  =========
  --  _AS       : Address Strobe
  --  _CE       : Clock Enable
  --  _CS       : Chip Select
  --  _DS       : Data Strobe
  --  _EN       : Enable
  --  _OE       : Output Enable
  --  _RD       : Read Select
  --  _WE       : Write Enable
  --  _WR       : Write Select
  --  _d[d...]  : Delayed (registered) signal (each 'd' denotes one 
  --              level of delay)
  --  _n        : Active low signals (must be last part of name)
  --
  --  Name                  Width  Dir*   Description
  --  ====================  =====  ====   ==============================
  --  Addr                   23     I     Address bus input (DWORD)
  --  Data_In                32     I     Data bus input
  --  Data_Out               32     O     Data bus output
  --  Reg_Strobe_n            1     I     Register access strobe
  --  Mem_Strobe_n            1     I     Memory access strobe
  --  Write_Sel_n             1     I     Write select
  --  Int_Req_n               1     O     Interrupt request
  --  DMA_Chan                2     I     DMA channel number indicator
  --  DMA_Stat                2     O     DMA channel status flags
  --
  --  * Direction 'O' means the user drives the signal, 'I' means the 
  --    pads drive the signal.
  --
  ----------------------------------------------------------------------
  type LAD_Bus_Std_IF_Type is record
    Addr          : std_logic_vector ( 22 downto 0 );
    Data_In       : std_logic_vector ( 31 downto 0 );
    Data_Out      : std_logic_vector ( 31 downto 0 );
    Reg_Strobe_n  : std_logic;
    Mem_Strobe_n  : std_logic;
    Write_Sel_n   : std_logic;
    Int_Req_n     : std_logic;
    DMA_Chan      : std_logic_vector ( 1 downto 0 );
    DMA_Stat      : std_logic_vector ( 1 downto 0 );
  end record;

  type LAD_Bus_Std_IF_In_Type is record
    Addr          : std_logic_vector ( 22 downto 0 );
    Data_In       : std_logic_vector ( 31 downto 0 );
    Reg_Strobe_n  : std_logic;
    Mem_Strobe_n  : std_logic;
    Write_Sel_n   : std_logic;
    DMA_Chan      : std_logic_vector ( 1 downto 0 );
  end record;

  type LAD_Bus_Std_IF_Out_Type is record
    Data_Out      : std_logic_vector ( 31 downto 0 );
    Int_Req_n     : std_logic;
    DMA_Stat      : std_logic_vector ( 1 downto 0 );
  end record;

  procedure Init_LAD_Bus_Std_IF
    (
      signal User : out LAD_Bus_Std_IF_Type
    );

  procedure Init_LAD_Bus_Std_IF
    (
      signal User : out LAD_Bus_Std_IF_In_Type
    );

  component LAD_Bus_Std_IF is
    port
    (
      K_Clk         : in    std_logic;
      Global_Reset  : in    std_logic;
      Pads          : inout LAD_Bus_Pads_Type;
      User_In       :   out LAD_Bus_Std_IF_In_Type;
      User_Out      : in    LAD_Bus_Std_IF_Out_Type
    );
  end component;

  ----------------------------------------------------------------------
  --
  --  LED_Std_IF_Type
  --
  --  Name Key:
  --  =========
  --  _AS       : Address Strobe
  --  _CE       : Clock Enable
  --  _CS       : Chip Select
  --  _DS       : Data Strobe
  --  _EN       : Enable
  --  _OE       : Output Enable
  --  _RD       : Read Select
  --  _WE       : Write Enable
  --  _WR       : Write Select
  --  _d[d...]  : Delayed (registered) signal (each 'd' denotes one 
  --              level of delay)
  --  _n        : Active low signals (must be last part of name)
  --
  --  Name                Width  Dir* Description
  --  ==================  =====  ==== ==================================
  --  Red_n                 1     O   Red light emitting diode output
  --  Green_n               1     O   Green light emitting diode output
  --
  --  * Direction 'O' means the user drives the signal, 'I' means the 
  --    pads drive the signal.
  --
  --
  ----------------------------------------------------------------------
  type LED_Std_IF_Type is record
    Red_n   : std_logic;
    Green_n : std_logic;
  end record;

  type LED_Std_IF_Out_Type is record
    Red_n   : std_logic;
    Green_n : std_logic;
  end record;

  procedure Init_LED_Std_IF
    (
      signal User : out LED_Std_IF_Type
    );

  component LED_Std_IF is
    port
    (
      Pads      : inout LED_Pads_Type;
      User_Out  : in    LED_Std_IF_Out_Type
    );
  end component;

  ----------------------------------------------------------------------
  --
  --  Mem_Std_IF_Type
  --
  --  Name Key:
  --  =========
  --  _AS       : Address Strobe
  --  _CE       : Clock Enable
  --  _CS       : Chip Select
  --  _DS       : Data Strobe
  --  _EN       : Enable
  --  _OE       : Output Enable
  --  _RD       : Read Select
  --  _WE       : Write Enable
  --  _WR       : Write Select
  --  _d[d...]  : Delayed (registered) signal (each 'd' denotes one 
  --              level of delay)
  --  _n        : Active low signals (must be last part of name)
  --
  --  Name                  Width  Dir*   Description
  --  ====================  =====  ====   ==============================
  --  Addr                   20     O     Address bus (DWORD)
  --  Data_In                32     I     Input data bus
  --  Data_Out               32     O     Output data bus
  --  Data_Valid_n            1     I     Valid read data flag
  --  Strobe_n                1     O     Memory cycle strobe
  --  Write_Sel_n             1     O     Write cycle select
  --
  --  * Direction 'O' means the user drives the signal, 'I' means the 
  --    pads drive the signal.
  --
  ----------------------------------------------------------------------
  type Mem_Std_IF_Type is record
    Addr          : std_logic_vector ( 19 downto 0 );
    Data_In       : std_logic_vector ( 31 downto 0 );
    Data_Out      : std_logic_vector ( 31 downto 0 );
    Data_Valid_n  : std_logic;
    Strobe_n      : std_logic;
    Write_Sel_n   : std_logic;
  end record;

  type Mem_Std_IF_In_Type is record
    Data_In       : std_logic_vector ( 31 downto 0 );
    Data_Valid_n  : std_logic;
  end record;

  type Mem_Std_IF_Out_Type is record
    Addr          : std_logic_vector ( 19 downto 0 );
    Data_Out      : std_logic_vector ( 31 downto 0 );
    Strobe_n      : std_logic;
    Write_Sel_n   : std_logic;
  end record;

  procedure Init_Mem_Std_IF
    (
      signal User : out Mem_Std_IF_Type
    );

  procedure Init_Mem_Std_IF
    (
      signal User : out Mem_Std_IF_In_Type
    );

  component Mem_Std_IF is
    generic
    (
      INFF_Delay    : INTEGER := NODELAY;
      OBUF_Drive    : INTEGER := SLOW_12mA
    );
    port
    (
      M_Clk         : in    std_logic;
      Global_Reset  : in    std_logic;
      Pads          : inout Mem_Pads_Type;
      User_In       :   out Mem_Std_IF_In_Type;
      User_Out      : in    Mem_Std_IF_Out_Type
    );
  end component;

  ----------------------------------------------------------------------
  --
  --  PE0_Bus_Std_IF_Type
  --
  --  Name Key:
  --  =========
  --  _AS       : Address Strobe
  --  _CE       : Clock Enable
  --  _CS       : Chip Select
  --  _DS       : Data Strobe
  --  _EN       : Enable
  --  _OE       : Output Enable
  --  _RD       : Read Select
  --  _WE       : Write Enable
  --  _WR       : Write Select
  --  _d[d...]  : Delayed (registered) signal (each 'd' denotes one 
  --              level of delay)
  --  _n        : Active low signals (must be last part of name)
  --
  --  Name                  Width  Dir*   Description
  --  ====================  =====  ====   ==============================
  --  Data_In                 2     I     Data input
  --  Data_Out                2     O     Data output
  --  Data_OE_n               2     O     Data output enable
  --
  --  * Direction 'O' means the user drives the signal, 'I' means the 
  --    pads drive the signal.
  --
  ----------------------------------------------------------------------
  type PE0_Bus_Std_IF_Type is record
    Data_In   : std_logic_vector ( 1 downto 0 );
    Data_Out  : std_logic_vector ( 1 downto 0 );
    Data_OE_n : std_logic_vector ( 1 downto 0 );
  end record;

  type PE0_Bus_Std_IF_In_Type is record
    Data_In   : std_logic_vector ( 1 downto 0 );
  end record;

  type PE0_Bus_Std_IF_Out_Type is record
    Data_Out  : std_logic_vector ( 1 downto 0 );
    Data_OE_n : std_logic_vector ( 1 downto 0 );
  end record;

  procedure Init_PE0_Bus_Std_IF
    (
      signal User : out PE0_Bus_Std_IF_Type
    );

  procedure Init_PE0_Bus_Std_IF
    (
      signal User : out PE0_Bus_Std_IF_In_Type
    );

  component PE0_Bus_Std_IF is
    generic
    (
      INFF_Delay    : INTEGER := NODELAY;
      OBUF_Drive    : INTEGER := FAST_8mA
    );
    port
    (
      Clk           : in    std_logic;
      Global_Reset  : in    std_logic;
      Pads          : inout PE0_Bus_Pads_Type;
      User_In       :   out PE0_Bus_Std_IF_In_Type;
      User_Out      : in    PE0_Bus_Std_IF_Out_Type
    );
  end component;

  ----------------------------------------------------------------------
  --
  --  Systolic_Std_IF_Type
  --
  --  Name Key:
  --  =========
  --  _AS       : Address Strobe
  --  _CE       : Clock Enable
  --  _CS       : Chip Select
  --  _DS       : Data Strobe
  --  _EN       : Enable
  --  _OE       : Output Enable
  --  _RD       : Read Select
  --  _WE       : Write Enable
  --  _WR       : Write Select
  --  _d[d...]  : Delayed (registered) signal (each 'd' denotes one 
  --              level of delay)
  --  _n        : Active low signals (must be last part of name)
  --
  --  Name                  Width  Dir*   Description
  --  ====================  =====  ====   ==============================
  --  Data_In                36     I     Data input
  --  Data_Out               36     O     Data output
  --  Data_OE_n              36     O     Data output enable
  --
  --  * Direction 'O' means the user drives the signal, 'I' means the 
  --    pads drive the signal.
  --
  ----------------------------------------------------------------------
  type Systolic_Std_IF_Type is record
    Data_In   : std_logic_vector ( 35 downto 0 );
    Data_Out  : std_logic_vector ( 35 downto 0 );
    Data_OE_n : std_logic_vector ( 35 downto 0 );
  end record;

  type Systolic_Std_IF_In_Type is record
    Data_In   : std_logic_vector ( 35 downto 0 );
  end record;

  type Systolic_Std_IF_Out_Type is record
    Data_Out  : std_logic_vector ( 35 downto 0 );
    Data_OE_n : std_logic_vector ( 35 downto 0 );
  end record;

  procedure Init_Systolic_Std_IF
    (
      signal User : out Systolic_Std_IF_Type
    );

  procedure Init_Systolic_Std_IF
    (
      signal User : out Systolic_Std_IF_In_Type
    );

  component Systolic_Std_IF is
    generic
    (
      INFF_Delay    : INTEGER := NODELAY;
      OBUF_Drive    : INTEGER := FAST_8mA
    );
    port
    (
      Clk           : in    std_logic;
      Global_Reset  : in    std_logic;
      Pads          : inout Systolic_Pads_Type;
      User_In       :   out Systolic_Std_IF_In_Type;
      User_Out      : in    Systolic_Std_IF_Out_Type
    );
  end component;

  ----------------------------------------------------------------------
  --
  --  IO_Conn_Std_IF_Type
  --
  --  Name Key:
  --  =========
  --  _AS       : Address Strobe
  --  _CE       : Clock Enable
  --  _CS       : Chip Select
  --  _DS       : Data Strobe
  --  _EN       : Enable
  --  _OE       : Output Enable
  --  _RD       : Read Select
  --  _WE       : Write Enable
  --  _WR       : Write Select
  --  _d[d...]  : Delayed (registered) signal (each 'd' denotes one 
  --              level of delay)
  --  _n        : Active low signals (must be last part of name)
  --
  --  Name                  Width  Dir*   Description
  --  ====================  =====  ====   ==============================
  --  Data_In                66     I     Data input
  --  Data_Out               66     O     Data output
  --  Data_OE_n              66     O     Data output enable
  --
  --  * Direction 'O' means the user drives the signal, 'I' means the 
  --    pads drive the signal.
  --
  ----------------------------------------------------------------------
  type IO_Conn_Std_IF_Type is record
    Data_In   : std_logic_vector ( 65 downto 0 );
    Data_Out  : std_logic_vector ( 65 downto 0 );
    Data_OE_n : std_logic_vector ( 65 downto 0 );
  end record;

  type IO_Conn_Std_IF_In_Type is record
    Data_In   : std_logic_vector ( 65 downto 0 );
  end record;

  type IO_Conn_Std_IF_Out_Type is record
    Data_Out  : std_logic_vector ( 65 downto 0 );
    Data_OE_n : std_logic_vector ( 65 downto 0 );
  end record;

  procedure Init_IO_Conn_Std_IF
    (
      signal User : out IO_Conn_Std_IF_Type
    );

  procedure Init_IO_Conn_Std_IF
    (
      signal User : out IO_Conn_Std_IF_In_Type
    );

  component IO_Conn_Std_IF is
    generic
    (
      INFF_Delay    : INTEGER := NODELAY;
      OBUF_Drive    : INTEGER := FAST_8mA
    );
    port
    (
      Clk           : in    std_logic;
      Global_Reset  : in    std_logic;
      Pads_Top_Sys  : inout Systolic_Pads_Type;
      Pads_Bot_Sys  : inout Systolic_Pads_Type;
      Pads_PE0_Bus  : inout PE0_Bus_Pads_Type;
      User_In       :   out IO_Conn_Std_IF_In_Type;
      User_Out      : in    IO_Conn_Std_IF_Out_Type
    );
  end component;

end package;

------------------------ Package Body Declaration ----------------------

package body PE_Package is

  ----------------------- Procedure Declarations -----------------------

  --@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
  --
  --  Pads Initialization Procedures
  --
  --@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@

  ----------------------------------------------------------------------