pe_pkg.vhd

arm9_fpga2_verilog是一个可以综合的用verilog写的arm9的ip软核

  ----------------------------------------------------------------------
  type Clock_Basic_IO_Type is record
    M_Clk : std_logic;
    P_Clk : std_logic;
    K_Clk : std_logic;
    U_Clk : std_logic;
  end record;

  type Clock_Basic_IO_In_Type is record
    M_Clk : std_logic;
    P_Clk : std_logic;
    K_Clk : std_logic;
    U_Clk : std_logic;
  end record;

  procedure Init_Clock_Basic_IO
    (
      signal User : out Clock_Basic_IO_Type
    );

  procedure Init_Clock_Basic_IO
    (
      signal User : out Clock_Basic_IO_In_Type
    );

  component Clock_Basic_IO is
    port
    (
      Pads      : inout Clock_Pads_Type;
      User_In   :   out Clock_Basic_IO_In_Type
    );
  end component;
  
  ----------------------------------------------------------------------
  --
  --  LAD_Bus_Basic_IO_Type
  --
  --  Name Key:
  --  =========
  --  _AS       : Address Strobe
  --  _CE       : Clock Enable
  --  _CS       : Chip Select
  --  _DS       : Data Strobe
  --  _EN       : Enable
  --  _OE       : Output Enable
  --  _RD       : Read Select
  --  _WE       : Write Enable
  --  _WR       : Write Select
  --  _d[d...]  : Delayed (registered) signal (each 'd' denotes one 
  --              level of delay)
  --  _n        : Active low signals (must be last part of name)
  --
  --  Name                  Width  Dir*   Description
  --  ====================  =====  ====   ==============================
  --  Addr_Data_In           32     I     Shared address/data bus input
  --  Addr_Data_Out          32     O     Shared address/data bus output
  --  Addr_Data_OE_n          1     O     Address/data bus output enable
  --  DS_n                    1     I     Data strobe
  --  Reg_n                   1     I     Register mode select
  --  WR_n                    1     I     Write select
  --  CS_n                    1     I     PE chip select
  --  Int_Req_n               1     O     Interrupt request
  --  DMA_Chan                2     I     DMA channel number indicator
  --  DMA_Stat                2     O     DMA channel status flags
  --
  --  * Direction 'O' means the user drives the signal, 'I' means the 
  --    pads drive the signal.
  --
  ----------------------------------------------------------------------
  type LAD_Bus_Basic_IO_Type is record
    Addr_Data_In    : std_logic_vector ( 31 downto 0 );
    Addr_Data_Out   : std_logic_vector ( 31 downto 0 );
    Addr_Data_OE_n  : std_logic_vector ( 31 downto 0 );
    DS_n            : std_logic;
    Reg_n           : std_logic;
    WR_n            : std_logic;
    CS_n            : std_logic;
    Int_Req_n       : std_logic;
    DMA_Chan        : std_logic_vector ( 1 downto 0 );
    DMA_Stat        : std_logic_vector ( 1 downto 0 );
  end record;

  type LAD_Bus_Basic_IO_In_Type is record
    Addr_Data_In    : std_logic_vector ( 31 downto 0 );
    DS_n            : std_logic;
    Reg_n           : std_logic;
    WR_n            : std_logic;
    CS_n            : std_logic;
    DMA_Chan        : std_logic_vector ( 1 downto 0 );
  end record;

  type LAD_Bus_Basic_IO_Out_Type is record
    Addr_Data_Out   : std_logic_vector ( 31 downto 0 );
    Addr_Data_OE_n  : std_logic_vector ( 31 downto 0 );
    Int_Req_n       : std_logic;
    DMA_Stat        : std_logic_vector ( 1 downto 0 );
  end record;

  procedure Init_LAD_Bus_Basic_IO
    (
      signal User : out LAD_Bus_Basic_IO_Type
    );

  procedure Init_LAD_Bus_Basic_IO
    (
      signal User : out LAD_Bus_Basic_IO_In_Type
    );

  component LAD_Bus_Basic_IO is
    port
    (
      Pads      : inout LAD_Bus_Pads_Type;
      User_In   :   out LAD_Bus_Basic_IO_In_Type;
      User_Out  : in    LAD_Bus_Basic_IO_Out_Type
    );
  end component;

  ----------------------------------------------------------------------
  --
  --  LED_Basic_IO_Type
  --
  --  Name Key:
  --  =========
  --  _AS       : Address Strobe
  --  _CE       : Clock Enable
  --  _CS       : Chip Select
  --  _DS       : Data Strobe
  --  _EN       : Enable
  --  _OE       : Output Enable
  --  _RD       : Read Select
  --  _WE       : Write Enable
  --  _WR       : Write Select
  --  _d[d...]  : Delayed (registered) signal (each 'd' denotes one 
  --              level of delay)
  --  _n        : Active low signals (must be last part of name)
  --
  --  Name                Width  Dir* Description
  --  ==================  =====  ==== ==================================
  --  Red_n                 1     O   Red light emitting diode output
  --  Green_n               1     O   Green light emitting diode output
  --
  --  * Direction 'O' means the user drives the signal, 'I' means the 
  --    pads drive the signal.
  --
  --
  ----------------------------------------------------------------------
  type LED_Basic_IO_Type is record
    Red_n   : std_logic;
    Green_n : std_logic;
  end record;

  type LED_Basic_IO_Out_Type is record
    Red_n   : std_logic;
    Green_n : std_logic;
  end record;

  procedure Init_LED_Basic_IO
    (
      signal User : out LED_Basic_IO_Type
    );

  component LED_Basic_IO is
    port
    (
      Pads      : inout LED_Pads_Type;
      User_Out  : in    LED_Basic_IO_Out_Type
    );
  end component;

  ----------------------------------------------------------------------
  --
  --  Mem_Basic_IO_Type
  --
  --  Name Key:
  --  =========
  --  _AS       : Address Strobe
  --  _CE       : Clock Enable
  --  _CS       : Chip Select
  --  _DS       : Data Strobe
  --  _EN       : Enable
  --  _OE       : Output Enable
  --  _RD       : Read Select
  --  _WE       : Write Enable
  --  _WR       : Write Select
  --  _d[d...]  : Delayed (registered) signal (each 'd' denotes one 
  --              level of delay)
  --  _n        : Active low signals (must be last part of name)
  --
  --  Name                  Width  Dir*   Description
  --  ====================  =====  ====   ==============================
  --  Addr                   19     O     Address bus output
  --  Data_In                32     I     Data bus input
  --  Data_Out               32     O     Data bus output
  --  Data_OE_n              32     O     Data bus output enable
  --  Addr_CS_n               1     O     Address chip select (extra
  --                                      addr line)
  --  CS_n                    1     O     Chip select
  --  WE_n                    1     O     Write enable
  --
  --  * Direction 'O' means the user drives the signal, 'I' means the 
  --    pads drive the signal.
  --
  ----------------------------------------------------------------------
  type Mem_Basic_IO_Type is record
    Addr      : std_logic_vector ( 18 downto 0 );
    Data_In   : std_logic_vector ( 31 downto 0 );
    Data_Out  : std_logic_vector ( 31 downto 0 );
    Data_OE_n : std_logic_vector ( 31 downto 0 );
    Addr_CS_n : std_logic;
    CS_n      : std_logic;
    WE_n      : std_logic;
  end record;

  type Mem_Basic_IO_In_Type is record
    Data_In   : std_logic_vector ( 31 downto 0 );
  end record;

  type Mem_Basic_IO_Out_Type is record
    Addr      : std_logic_vector ( 18 downto 0 );
    Data_Out  : std_logic_vector ( 31 downto 0 );
    Data_OE_n : std_logic_vector ( 31 downto 0 );
    Addr_CS_n : std_logic;
    CS_n      : std_logic;
    WE_n      : std_logic;
  end record;

  procedure Init_Mem_Basic_IO
    (
      signal User : out Mem_Basic_IO_Type
    );

  procedure Init_Mem_Basic_IO
    (
      signal User : out Mem_Basic_IO_In_Type
    );

  component Mem_Basic_IO is
    generic
    (
      INFF_Delay    : INTEGER := NODELAY;
      OBUF_Drive    : INTEGER := SLOW_12mA
    );
    port
    (
      Pads      : inout Mem_Pads_Type;
      User_In   :   out Mem_Basic_IO_In_Type;
      User_Out  : in    Mem_Basic_IO_Out_Type
    );
  end component;

  ----------------------------------------------------------------------
  --
  --  PE0_Bus_Basic_IO_Type
  --
  --  Name Key:
  --  =========
  --  _AS       : Address Strobe
  --  _CE       : Clock Enable
  --  _CS       : Chip Select
  --  _DS       : Data Strobe
  --  _EN       : Enable
  --  _OE       : Output Enable
  --  _RD       : Read Select
  --  _WE       : Write Enable
  --  _WR       : Write Select
  --  _d[d...]  : Delayed (registered) signal (each 'd' denotes one 
  --              level of delay)
  --  _n        : Active low signals (must be last part of name)
  --
  --  Name                  Width  Dir*   Description
  --  ====================  =====  ====   ==============================
  --  Data_In                 2     I     Data input
  --  Data_Out                2     O     Data output
  --  Data_OE_n               2     O     Data output enable
  --
  --  * Direction 'O' means the user drives the signal, 'I' means the 
  --    pads drive the signal.
  --
  ----------------------------------------------------------------------
  type PE0_Bus_Basic_IO_Type is record
    Data_In   : std_logic_vector ( 1 downto 0 );
    Data_Out  : std_logic_vector ( 1 downto 0 );
    Data_OE_n : std_logic_vector ( 1 downto 0 );
  end record;

  type PE0_Bus_Basic_IO_In_Type is record
    Data_In   : std_logic_vector ( 1 downto 0 );
  end record;

  type PE0_Bus_Basic_IO_Out_Type is record
    Data_Out  : std_logic_vector ( 1 downto 0 );
    Data_OE_n : std_logic_vector ( 1 downto 0 );
  end record;

  procedure Init_PE0_Bus_Basic_IO
    (
      signal User : out PE0_Bus_Basic_IO_Type
    );

  procedure Init_PE0_Bus_Basic_IO
    (
      signal User : out PE0_Bus_Basic_IO_In_Type
    );

  component PE0_Bus_Basic_IO is
    generic
    (
      INFF_Delay    : INTEGER := NODELAY;
      OBUF_Drive    : INTEGER := FAST_8mA
    );
    port
    (
      Pads      : inout PE0_Bus_Pads_Type;
      User_In   :   out PE0_Bus_Basic_IO_In_Type;
      User_Out  : in    PE0_Bus_Basic_IO_Out_Type
    );
  end component;

  ----------------------------------------------------------------------
  --
  --  Systolic_Basic_IO_Type
  --
  --  Name Key:
  --  =========
  --  _AS       : Address Strobe
  --  _CE       : Clock Enable
  --  _CS       : Chip Select
  --  _DS       : Data Strobe
  --  _EN       : Enable
  --  _OE       : Output Enable
  --  _RD       : Read Select
  --  _WE       : Write Enable
  --  _WR       : Write Select
  --  _d[d...]  : Delayed (registered) signal (each 'd' denotes one 
  --              level of delay)
  --  _n        : Active low signals (must be last part of name)
  --
  --  Name                  Width  Dir*   Description
  --  ====================  =====  ====   ==============================
  --  Data_In                36     I     Data input
  --  Data_Out               36     O     Data output
  --  Data_OE_n              36     O     Data output enable
  --
  --  * Direction 'O' means the user drives the signal, 'I' means the 
  --    pads drive the signal.
  --
  ----------------------------------------------------------------------
  type Systolic_Basic_IO_Type is record
    Data_In   : std_logic_vector ( 35 downto 0 );
    Data_Out  : std_logic_vector ( 35 downto 0 );
    Data_OE_n : std_logic_vector ( 35 downto 0 );
  end record;

  type Systolic_Basic_IO_In_Type is record
    Data_In   : std_logic_vector ( 35 downto 0 );
  end record;

  type Systolic_Basic_IO_Out_Type is record
    Data_Out  : std_logic_vector ( 35 downto 0 );
    Data_OE_n : std_logic_vector ( 35 downto 0 );
  end record;

  procedure Init_Systolic_Basic_IO
    (
      signal User : out Systolic_Basic_IO_Type
    );

  procedure Init_Systolic_Basic_IO
    (
      signal User : out Systolic_Basic_IO_In_Type
    );

  component Systolic_Basic_IO is
    generic
    (
      INFF_Delay    : INTEGER := NODELAY;
      OBUF_Drive    : INTEGER := FAST_8mA
    );
    port
    (
      Pads      : inout Systolic_Pads_Type;
      User_In   :   out Systolic_Basic_IO_In_Type;
      User_Out  : in    Systolic_Basic_IO_Out_Type
    );
  end component;

  --@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
  --
  --  Standard Interface Types, Components, and Procedures
  --
  --@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@

  ----------------------------------------------------------------------
  --
  --  Clock_Std_IF_Type
  --
  --  Name Key:
  --  =========
  --  _AS       : Address Strobe
  --  _CB       : CardBus
  --  _CE       : Clock Enable
  --  _CS       : Chip Select
  --  _DS       : Data Strobe
  --  _EN       : Enable
  --  _OE       : Output Enable
  --  _PE       : Processing Element
  --  _RD       : Read Select
  --  _WE       : Write Enable
  --  _WR       : Write Select
  --  _d[d...]  : Delayed (registered) signal (each 'd' denotes one 
  --              level of delay)
  --  _n        : Active low signals (must be last part of name)
  --
  --  Name                  Width  Dir*   Description
  --  ====================  =====  ====   ==============================
  --  M_Clk                   1     I     Memory clock
  --  P_Clk                   1     I     Processing element clock
  --  K_Clk                   1     I     LAD-bus clock
  --  U_Clk                   1     I     User clock
  --  M_Clk_Locked            1     I     M_Clk CLKDLL locked flag
  --  P_Clk_Locked            1     I     P_Clk CLKDLL locked flag
  --  K_Clk_Locked            1     I     K_Clk CLKDLL locked flag
  --  U_Clk_Locked            1     I     U_Clk CLKDLL locked flag
  --  
  --  * Direction 'O' means the user drives the signal, 'I' means the 
  --    pads drive the signal.
  --
  ----------------------------------------------------------------------
  type Clock_Std_IF_Type is record
    M_Clk         : std_logic;
    P_Clk         : std_logic;
    K_Clk         : std_logic;
    U_Clk         : std_logic;
    M_Clk_Locked  : std_logic;
    P_Clk_Locked  : std_logic;
    K_Clk_Locked  : std_logic;
    U_Clk_Locked  : std_logic;
  end record;

  type Clock_Std_IF_In_Type is record
    M_Clk         : std_logic;
    P_Clk         : std_logic;
    K_Clk         : std_logic;
    U_Clk         : std_logic;
    M_Clk_Locked  : std_logic;
    P_Clk_Locked  : std_logic;
    K_Clk_Locked  : std_logic;
    U_Clk_Locked  : std_logic;
  end record;

  procedure Init_Clock_Std_IF
    (
      signal User : out Clock_Std_IF_Type
    );

  procedure Init_Clock_Std_IF
    (
      signal User : out Clock_Std_IF_In_Type