mmu_new.v

arm9_fpga2_verilog是一个可以综合的用verilog写的arm9的ip软核

    if (~nRESET)
      cr8 <= 32'h0;
    else if (nWAIT)
      begin
        if (write_cr8)
          cr8 <= res_to_wb;
      end
  end

assign write_cr9 = rfw_ena & (CRd_cme == 4'h9);
//synopsys async_set_reset "nRESET"
always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      cr9 <= 32'h0;
    else if (nWAIT)
      begin
        if (write_cr9)
          cr9 <= res_to_wb;
      end
  end

assign write_cr10 = rfw_ena & (CRd_cme == 4'ha);
//synopsys async_set_reset "nRESET"
always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      cr10 <= 32'h0;
    else if (nWAIT)
      begin
        if (write_cr10)
          cr10 <= res_to_wb;
      end
  end

assign write_cr11 = rfw_ena & (CRd_cme == 4'hb);
//synopsys async_set_reset "nRESET"
always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      cr11 <= 32'h0;
    else if (nWAIT)
      begin
        if (write_cr11)
          cr11 <= res_to_wb;
      end
  end

assign write_cr12 = rfw_ena & (CRd_cme == 4'hc);
//synopsys async_set_reset "nRESET"
always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      cr12 <= 32'h0;
    else if (nWAIT)
      begin
        if (write_cr12) 
          cr12 <= res_to_wb;
      end   
  end

assign write_cr13 = rfw_ena & (CRd_cme == 4'hd);
//synopsys async_set_reset "nRESET"
always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      cr13 <= 32'h0;
    else if (nWAIT)
      begin
        if (write_cr13)
          cr13 <= res_to_wb;
      end
  end

assign write_cr14 = rfw_ena & (CRd_cme == 4'he);
//synopsys async_set_reset "nRESET"
always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      cr14 <= 32'h0;
    else if (nWAIT)
      begin
        if (DABORT)
          cr14 <= da;
      end
  end

assign write_cr15 = rfw_ena & (CRd_cme == 4'hf);
//synopsys async_set_reset "nRESET"
always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      cr15 <= 32'h0;
    else if (nWAIT)
      begin
        if (DABORT)
          cr15 <= da;
      end
  end

//Read the Proper Operands
always @(cr0 or cr1 or cr2 or cr3 or cr4 or cr5 or cr6 or cr7 or cr8 or
	 cr9 or cr10 or cr11 or cr12 or cr13 or cr14 or cr15 or 
	 op1_index_cid)
  begin
    case (op1_index_cid) //synopsys full_case parallel_case
      4'h0: rf_op1 = cr0;
      4'h1: rf_op1 = cr1;
      4'h2: rf_op1 = cr2;
      4'h3: rf_op1 = cr3;
      4'h4: rf_op1 = cr4;
      4'h5: rf_op1 = cr5;
      4'h6: rf_op1 = cr6;
      4'h7: rf_op1 = cr7;
      4'h8: rf_op1 = cr8;
      4'h9: rf_op1 = cr9;
      4'ha: rf_op1 = cr10;
      4'hb: rf_op1 = cr11;
      4'hc: rf_op1 = cr12;
      4'hd: rf_op1 = cr13;
      4'he: rf_op1 = cr14;
      4'hf: rf_op1 = cr15;
    endcase
  end

always @(op1_index_cid or inst_count or cyc_count or imiss_count
                or dmiss_count or iaccesses or daccesses or time_count or
		predicted or pcorrect or spec_iabort or spec_dabort)
  begin
    case (op1_index_cid) //synopsys full_case parallel_case
      4'h0: perf_op1 = inst_count;
      4'h1: perf_op1 = cyc_count;
      4'h2: perf_op1 = imiss_count;
      4'h3: perf_op1 = dmiss_count;
      4'h4: perf_op1 = iaccesses;
      4'h5: perf_op1 = daccesses;
      4'h6: perf_op1 = predicted;
      4'h7: perf_op1 = pcorrect;
      4'h8: perf_op1 = spec_iabort;
      4'h9: perf_op1 = spec_dabort;
      4'hA: perf_op1 = time_count;
   default: perf_op1 = inst_count;
    endcase
  end



always @(cr0 or cr1 or cr2 or cr3 or cr4 or cr5 or cr6 or cr7 or cr8 or
         cr9 or cr10 or cr11 or cr12 or cr13 or cr14 or cr15 or 
	 op2_index_cid)
begin
    case (op2_index_cid) //synopsys full_case parallel_case
      4'h0: rf_op2 = cr0;
      4'h1: rf_op2 = cr1;
      4'h2: rf_op2 = cr2;
      4'h3: rf_op2 = cr3;
      4'h4: rf_op2 = cr4;
      4'h5: rf_op2 = cr5;
      4'h6: rf_op2 = cr6;
      4'h7: rf_op2 = cr7;
      4'h8: rf_op2 = cr8;
      4'h9: rf_op2 = cr9;
      4'ha: rf_op2 = cr10;
      4'hb: rf_op2 = cr11;
      4'hc: rf_op2 = cr12;
      4'hd: rf_op2 = cr13;
      4'he: rf_op2 = cr14;
      4'hf: rf_op2 = cr15;
    endcase
  end

/*------------------------------------------------------------------*/
/* Instruction Decompression Trigger Circuitry                      */
/*------------------------------------------------------------------*/

//Latch the Address Bus
always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      ia <= 26'h0;
    else if (nWAIT)
      begin
        if (~InMREQ)
          ia <= IA[31:6];
      end
  end

always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      da <= 32'h0;
    else if (nWAIT)
      begin
        if (~DnMREQ)
          da <= DA[31:0];
      end
  end

/* First Compare the Top 21 Bits */
wire	[31:11]	inst_xor0;	//Bitwise XOR of Top 21 Bits
wire	[31:11]	inst_xor1;	//Bitwise XOR of Top 21 Bits
wire	[31:11] inst_xor2;	//Bitwise XOR of Top 21 Bits
wire	[31:11] data_xor0;	//Bitwise XOR or Top 21 DA Bits
wire    [31:11] data_xor1;      //Bitwise XOR or Top 21 DA Bits
wire    [31:11] data_xor2;      //Bitwise XOR or Top 21 DA Bits
wire	[31:11]	cbrtag0;	//Tag of Region 0
wire	[31:11] cbrtag1;	//Tag of Region 1
wire	[31:11]	cbrtag2;	//Tag of Region 2
wire	[31:6]  idrtag;		//Tag of Inst Decomp Routine 
wire	[31:11] abus;		//Address From IA Bus
wire	[31:11] dbus;		//Address from DA Bus
wire	[31:6]  addr_xor3;	//Bitwise XOR of Top 26 Bits

assign cbrtag0 = cr2[31:11];
assign cbrtag1 = cr3[31:11];
assign cbrtag2 = cr4[31:11];
assign idrtag = cr5[31:6];
assign abus = ia[31:11];
assign dbus = da[31:11];
assign inst_xor0 = (abus ^ cbrtag0);
assign inst_xor1 = (abus ^ cbrtag1);
assign inst_xor2 = (abus ^ cbrtag2);
assign data_xor0 = (dbus ^ cbrtag0);
assign data_xor1 = (dbus ^ cbrtag1);
assign data_xor2 = (dbus ^ cbrtag2);
assign addr_xor3 = (ia ^ idrtag);

/* Also Must Create the Size Masks */
/* Sizes Range from 2kB - 64MB in by powers of 2. */
/* 2kB = 0000, 4kB = 0001, 8kB = 0010, ... 64MB = 1111 */
/* 2kB check IA[31:11], 4kB check IA[31:12] ... 64MB check IA[31:26] */
reg	[31:11]	mask0;		//0 the Bits Comparing
reg	[31:11] mask1;		//0 the Bits Comparing
reg	[31:11] mask2;		//0 the Bits Comparing
reg	[31:6]	mask3;		//0 the Bist Comparing
wire	[3:0]	size0;		//Size of Region 0;
wire	[3:0]	size1;		//Size of Region 1;
wire	[3:0]	size2;		//Size of Region 2;
wire	[1:0]	size3;		//Size of Inst Decomp Routine

/* Split of the Sizes from the CBRR's */
assign size0 = cr2[3:0];
assign size1 = cr3[3:0];
assign size2 = cr4[3:0];
assign size3 = cr5[1:0];

/* Set up the Rest of each Mask */
always @(size0)
  begin
    case (size0) //synopsys full_case parallel_case
      4'h0: mask0[31:11] = 21'h000000;
      4'h1: mask0[31:11] = 21'h000001;
      4'h2: mask0[31:11] = 21'h000003;
      4'h3: mask0[31:11] = 21'h000007;
      4'h4: mask0[31:11] = 21'h00000F;
      4'h5: mask0[31:11] = 21'h00001F;
      4'h6: mask0[31:11] = 21'h00003F;
      4'h7: mask0[31:11] = 21'h00007F;
      4'h8: mask0[31:11] = 21'h0000FF;
      4'h9: mask0[31:11] = 21'h0001FF;
      4'hA: mask0[31:11] = 21'h0003FF;
      4'hB: mask0[31:11] = 21'h0007FF;
      4'hC: mask0[31:11] = 21'h000FFF;
      4'hD: mask0[31:11] = 21'h001FFF;
      4'hE: mask0[31:11] = 21'h003FFF;
      4'hF: mask0[31:11] = 21'h007FFF;
    endcase
  end

always @(size1)
  begin
    case (size1) //synopsys full_case parallel_case
      4'h0: mask1[31:11] = 21'h0000;
      4'h1: mask1[31:11] = 21'h0001;
      4'h2: mask1[31:11] = 21'h0003;
      4'h3: mask1[31:11] = 21'h0007;
      4'h4: mask1[31:11] = 21'h000F;
      4'h5: mask1[31:11] = 21'h001F;
      4'h6: mask1[31:11] = 21'h003F;
      4'h7: mask1[31:11] = 21'h007F;
      4'h8: mask1[31:11] = 21'h00FF;
      4'h9: mask1[31:11] = 21'h01FF;
      4'hA: mask1[31:11] = 21'h03FF;
      4'hB: mask1[31:11] = 21'h07FF;
      4'hC: mask1[31:11] = 21'h0FFF;
      4'hD: mask1[31:11] = 21'h1FFF;
      4'hE: mask1[31:11] = 21'h3FFF;
      4'hF: mask1[31:11] = 21'h7FFF;
    endcase
  end

always @(size2)
  begin
    case (size2) //synopsys full_case parallel_case
      4'h0: mask2[31:11] = 21'h0000;
      4'h1: mask2[31:11] = 21'h0001;
      4'h2: mask2[31:11] = 21'h0003;
      4'h3: mask2[31:11] = 21'h0007;
      4'h4: mask2[31:11] = 21'h000F;
      4'h5: mask2[31:11] = 21'h001F;
      4'h6: mask2[31:11] = 21'h003F;
      4'h7: mask2[31:11] = 21'h007F;
      4'h8: mask2[31:11] = 21'h00FF;
      4'h9: mask2[31:11] = 21'h01FF;
      4'hA: mask2[31:11] = 21'h03FF;
      4'hB: mask2[31:11] = 21'h07FF;
      4'hC: mask2[31:11] = 21'h0FFF;
      4'hD: mask2[31:11] = 21'h1FFF;
      4'hE: mask2[31:11] = 21'h3FFF;
      4'hF: mask2[31:11] = 21'h7FFF;
    endcase
  end

always @(size3)
  begin
    case (size3) //synopsys full_case parallel_case
      2'h0: mask3[31:6] = 26'h0000000;
      2'h1: mask3[31:6] = 26'h0000001;
      2'h2: mask3[31:6] = 26'h0000003;
      2'h3: mask3[31:6] = 26'h0000007;
    endcase
  end

/* XOR the AND'd address with the Mask and Or it     */
/* When nHit goes Low, there is a match              */
/* A match indicates an address in Compressed Region */
wire nHit0, nHit1, nHit2, nHit3, nHit4, nHit5, nHit6;
assign nHit0 = | (~mask0 & inst_xor0);
assign nHit1 = | (~mask1 & inst_xor1);
assign nHit2 = | (~mask2 & inst_xor2);
assign nHit3 = | (~mask3 & addr_xor3);
assign nHit4 = | (~mask0 & data_xor0);
assign nHit5 = | (~mask1 & data_xor1);
assign nHit6 = | (~mask2 & data_xor2);

/* Generate the Instruction Abort Interrupt */
assign IABORT = ((~nHit0 & cbrr0e & imiss) | 
		 (~nHit1 & cbrr1e & imiss) |
		 (~nHit2 & cbrr2e & imiss));

always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      abort_id <= 1'b0;
    else if (nWAIT)
      begin
        if (~id_enbar)
          abort_id <= (IABORT | DABORT);  
      end
  end

always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      abort_ex <= 1'b0;
    else if (nWAIT)
      begin
	if (~ex_enbar)
          abort_ex <= abort_id | (abort_ex & (mode == 5'b10111));
      end
  end
           
always @(posedge nGCLK or negedge nRESET)  
  begin
    if (~nRESET)
      abort_me <= 1'b0;
    else if (nWAIT)
      begin
        if (~me_enbar)
          abort_me <= abort_ex;
      end
  end

assign DABORT = ((~nHit4 & cbrr0e & dmiss & ~abort_me) |
                 (~nHit5 & cbrr1e & dmiss & ~abort_me) |
                 (~nHit6 & cbrr2e & dmiss & ~abort_me));
  
/* Generate Non-Cacheable Signal */
assign useMini = ~nHit3 & idrre;

endmodule