mmu_new.v

arm9_fpga2_verilog是一个可以综合的用verilog写的arm9的ip软核

  end

//Grab the Operand Indexes
assign CRn_cid = mmu_ir_id[19:16];
assign Rd_cid = mmu_ir_id[15:12];
assign CRm_cid = mmu_ir_id[3:0];
assign op1_index_cid = (mem_op_cid) ? Rd_cid : CRn_cid;
assign cop15 = (mmu_ir_id[11:8] == 4'hf);
assign N = mmu_ir_id[22];

//Decode the three types of Coprocessor Operations
assign mem_op_cid = (mmu_ir_id[27:25] == 3'h6) & cop15;
assign reg_op_cid = (mmu_ir_id[27:24] == 4'hE) &
                        (mmu_ir_id[4]) & cop15;
assign data_op_cid = (mmu_ir_id[27:24] == 4'hE) &
                        (~mmu_ir_id[4]) & cop15;

/* Modifying the coding of a SWIC, its now a Cop Store with N Set */
assign swic_cid = (mem_op_cid & N) & useMini;

/* Creating a Flush Instruction from Standard CDP */
assign flush_cid = (mem_op_cid & N) & ~useMini;

/* Creating a Move of Performance Counters */
assign move_perf = reg_op_cid & (mmu_ir_id[23:21] == 3'h7);

//Mux the 1st Operand Index  
always @(CRm_cid or Rd_cid or mem_op_cid or swic_cid)
  begin
    if (mem_op_cid)
      op2_index_cid = Rd_cid;
    else
      op2_index_cid = CRm_cid;
  end   

//Figure Out when to Interlock the Pipelie
//1) ARM is Interlocked
//2) Load-Use Interlock
assign load_use_op1 = (((mem_op_cid & ~mmu_ir_id[20]) 	| 
			reg_op_cid 			|
                        data_op_cid) 			&
        ((CRd_cex == op1_index_cid) & ~drive_DD_cex & mem_op_cex));

assign must_wait_cid = id_enbar | load_use_op1;


//Figure out how to drive CHSD
always @(reg_op_cid or mem_op_cid or data_op_cid or must_wait_cid)
  begin
    case({reg_op_cid,mem_op_cid,data_op_cid}) //synopsys full_case parallel_case
      3'b001: next_chsd = (must_wait_cid) ? 2'b00 : 2'b11;
      3'b010: next_chsd = (must_wait_cid) ? 2'b00 : 2'b11;   
      3'b100: next_chsd = (must_wait_cid) ? 2'b00 : 2'b11;   
      3'b000: next_chsd = 2'b10;
    endcase
  end 

//Probably don't need latch...just assign to next_chsd
//Latch the CHSD Signal
//synopsys async_set_reset "nRESET"
always @(nGCLK or next_chsd or nRESET or CHSD or nWAIT)
  begin
    if (~nRESET)
      CHSD <= #1 2'b10;
    else if (nGCLK)
      begin
        if (nWAIT)
//        CHSD <= #1 next_chsd;
          CHSD <= 2'b11;
	else
	  CHSD <= #1 CHSD;
      end
  end

//Mux out Operand 1
always @(op1_index_cid or CRd_cme or rf_op1 or res_to_wb or
		move_perf or perf_op1)
  begin
    if (move_perf)
      op1_cid = perf_op1;
    else if (op1_index_cid == CRd_cme)
      op1_cid = res_to_wb;
    else
      op1_cid = rf_op1;
  end

always @(rf_op2)
  begin
    op2_cid = rf_op2;
  end

/*------------------------------------------------------------------------
        MMU Ex Stage
------------------------------------------------------------------------*/
//Set up the Pipeline Status/Decode Bits
//synopsys async_set_reset "nRESET"
always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      begin
        mem_op_cex <= 1'b0;
        reg_op_cex <= 1'b0;
        data_op_cex <= 1'b0;
        drive_DD_cex <= 1'b0;
	swic_cex <= 1'b0;
        flush_cex <= 1'b0;
	op1_cex <= 32'h00000000;
	op2_cex <= 32'h00000000;
	CRd_cex <= 4'h0;
	op1_index_cex <= 4'h0;
      end
    else if (nWAIT)
      begin
        if (~ex_enbar)
          begin
            mem_op_cex <= mem_op_cid;
            reg_op_cex <= reg_op_cid;
            data_op_cex <= data_op_cid;
            drive_DD_cex <= (mmu_ir_id[20] & reg_op_cid) |
	    		    (~mmu_ir_id[20] & mem_op_cid);
	    swic_cex <= swic_cid;
            flush_cex <= flush_cid;
	    op1_cex <= op1_cid;
	    op2_cex <= op2_cid;
	    CRd_cex <= (reg_op_cid) ? CRn_cid : Rd_cid;
	    op1_index_cex <= op1_index_cid;
          end
      end
  end

/* Cop Instructions Only Executed it PASS is High */
/* Use me_enbar so that incorrect instructions (wrong branch path) */
/* Dont get executed */

assign iswic = swic_cex & swicInD & PASS & ~me_enbar;
assign dswic = swic_cex & ~swicInD & PASS & ~me_enbar;
assign dflush = flush_cex & PASS & ~me_enbar;
assign swic_data = res_cex;
assign decomp = useMini;

//synopsys async_set_reset "nRESET"
always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      load_use_cex <= 1'b0;
    else if (nWAIT)
      load_use_cex <= load_use_op1;
  end

//Determine the Result
always @(reg_op_cex or data_op_cex or drive_DD_cex or op1_cex or
                op1_index_cex or CRd_cme or res_to_wb or mem_op_cex or
                rfw_ena or data_op_cex or flush_cex)
  begin
    if ((reg_op_cex & drive_DD_cex) | (mem_op_cex & drive_DD_cex) | (data_op_cex))
      begin
        if ((op1_index_cex == CRd_cme) & rfw_ena & ~flush_cex)  //forward operand?
	  res_cex = res_to_wb;
        else
         res_cex = op1_cex;
      end
    else
      res_cex = 32'h00000000;
  end

//Figure out how to drive CHSD
assign must_wait_cex = id_enbar & ~load_use_cex;

always @(reg_op_cex or mem_op_cex or data_op_cex or must_wait_cex)
  begin
    case({reg_op_cex,mem_op_cex,data_op_cex}) //synopsys full_case parallel_case
      3'b001: next_chse = (must_wait_cex) ? 2'b00 : 2'b11;
      3'b010: next_chse = (must_wait_cex) ? 2'b00 : 2'b11;
      3'b100: next_chse = (must_wait_cex) ? 2'b00 : 2'b11;
      3'b000: next_chse = 2'b10;
    endcase
  end

//Probably don't need latch...just assign to next_chsd
//Latch the CHSE Signal
//synopsys async_set_reset "nRESET"
always @(nGCLK or next_chse or nRESET or nWAIT or CHSE)
  begin
    if (~nRESET)
      CHSE <= #1 2'b10;
    else if (nGCLK)
      begin
        if (nWAIT)
          CHSE <= #1 next_chse;
	else
	  CHSE <= CHSE;
      end
  end


/*------------------------------------------------------------------------
        MMU ME Stage     
------------------------------------------------------------------------*/
//synopsys async_set_reset "nRESET"
always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      begin
        mem_op_cme <= 1'b0;
        reg_op_cme <= 1'b0;
        data_op_cme <= 1'b0;
        drive_DD_cme <= 1'b0;
	CRd_cme <= 4'h0;
      end
    else if (nWAIT)
      begin
        if (~me_enbar)
          begin
            mem_op_cme <= mem_op_cex & PASS;
            reg_op_cme <= reg_op_cex & PASS;
            data_op_cme <= data_op_cex & PASS;
            drive_DD_cme <= drive_DD_cex & PASS;
	    CRd_cme <= CRd_cex;
	  end
      end
  end

//synopsys async_set_reset "nRESET"
always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      res_cme <= 32'h0;
    else if (nWAIT)
      res_cme <= res_cex;
  end

//Set up the DD data_bus
assign to_DD = res_cme;
assign DD = (drive_DD_cme) ? {32'h0,to_DD} : 64'hzzzzzzzzzzzzzzzz;

//Setup of the Result of ME Stage
always @(reg_op_cme or drive_DD_cme or DD or mem_op_cme or data_op_cme or
		res_cme)
  begin
    case({reg_op_cme,mem_op_cme,data_op_cme}) //synopsys full_case parallel_case
      3'b001: res_to_wb = res_cme;
      3'b010: res_to_wb = DD;
      3'b100: res_to_wb = DD;
      3'b000: res_to_wb = res_cme;
    endcase
  end

/*------------------------------------------------------------------------
        MMU WB Stage
------------------------------------------------------------------------*/
/*------------------------------------------------------------------------
        MMU Register File & Operand Access
------------------------------------------------------------------------*/
//Set up the ID Register
assign cr0 = 32'hED019ED0;

// Set up the Control Register
//	31:17	16	15:13	12:0
//Cr1 = O's	IDRRE	CBRRE's	IZFRSBLDPWCAM

//M= MMU Enable
//A= Alignment Fault Enable
//C= Data Cache Enable 
//W= Write Buffer Enable
//P= 32-Bit Exceptions (sb1)
//D= 32-Bit Addresses (sb1)
//L= --
//B= Big Endian=1/Little Endian=0
//S= System Protection
//R= ROM Protection
//F= --
//Z= --
//I= Instruction Cache Enable
//IDRRE - Instruction Decompression Routine Region enable
//	16 - Enable IDRR - cr5 (1=enabled)
//CBRRE's, Compression Boundary Region Register enables
//	15 - Enable CBRR2 - cr4 (1=enabled)
//	14 - Enable CBRR1 - cr3 (1=enabled)
//	13 - Enable CBRR0 - cr2 (1=enabled)

assign rfw_ena = ((reg_op_cme & ~drive_DD_cme) | 
		  (mem_op_cme & ~drive_DD_cme)) & ~LATECANCEL;

assign write_cr1 = rfw_ena && (CRd_cme == 4'h1);
assign BIGEND = cr1[7];
wire idrre = cr1[16];
wire cbrr2e = cr1[15];
wire cbrr1e = cr1[14];
wire cbrr0e = cr1[13];
//synopsys async_set_reset "nRESET"
always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      cr1 <= 32'h0;
    else if (nWAIT)
      begin
        if (write_cr1)
          cr1 <= res_to_wb;
      end
  end

assign write_cr2 = rfw_ena & (CRd_cme == 4'h2);
//synopsys async_set_reset "nRESET"
always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      cr2 <= 32'h0;
    else if (nWAIT)
      begin
        if (write_cr2)
          cr2 <= res_to_wb;
      end
  end

assign write_cr3 = rfw_ena & (CRd_cme == 4'h3);
//synopsys async_set_reset "nRESET"
always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      cr3 <= 32'h0;
    else if (nWAIT)
      begin
        if (write_cr3)
          cr3 <= res_to_wb;
      end
  end

assign write_cr4 = rfw_ena & (CRd_cme == 4'h4);
//synopsys async_set_reset "nRESET"
always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      cr4 <= 32'h0;
    else if (nWAIT)
      begin
        if (write_cr4)
          cr4 <= res_to_wb;
      end
  end

assign write_cr5 = rfw_ena & (CRd_cme == 4'h5);
//synopsys async_set_reset "nRESET"
always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      cr5 <= 32'h0;
    else if (nWAIT)
      begin
        if (write_cr5)
          cr5 <= res_to_wb;
      end
  end

assign write_cr6 = rfw_ena & (CRd_cme == 4'h6);
//synopsys async_set_reset "nRESET"
always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      cr6 <= 32'h0;
    else if (nWAIT)
      begin
        if (write_cr6)
          cr6 <= res_to_wb;
      end
  end

assign write_cr7 = rfw_ena & (CRd_cme == 4'h7);
//synopsys async_set_reset "nRESET"
always @(posedge nGCLK or negedge nRESET)
  begin
    if (~nRESET)
      cr7 <= 32'h0;
    else if (nWAIT)
      begin
        if (write_cr7)
          cr7 <= res_to_wb;
      end
  end

assign write_cr8 = rfw_ena & (CRd_cme == 4'h8);
//synopsys async_set_reset "nRESET"
always @(posedge nGCLK or negedge nRESET)
  begin