pex_mezz_mem_if_entarch.vhd

arm9_fpga2_verilog是一个可以综合的用verilog写的arm9的ip软核

      Shunt,
      Shunt_dd,
      Data_Out_dd,
      Write_dd
    )
    variable v_shunt_out : std_logic_vector ( 63 downto 0 );
    variable v_shunt_oe_n : std_logic_vector ( 63 downto 0 );
  begin

    if ( Shunt = '0' ) then
      Mem_User_Out.Addr_Out <= To_X01 ( User_Out.Addr(19 downto 17) & User_Out.Addr(15 downto 0) );
      Mem_User_Out.Addr_OE_n <= ( others => '0' );
      Mem_User_Out.Addr_CS_Out_n <= To_X01 ( User_Out.Addr(16) );
      Mem_User_Out.Addr_CS_OE_n <= '0';
      Mem_User_Out.Low_CS_Out_n <= To_X01 ( User_Out.Low_Strobe_n );
      Mem_User_Out.Low_CS_OE_n <= '0';
      Mem_User_Out.High_CS_Out_n <= To_X01 ( User_Out.High_Strobe_n );
      Mem_User_Out.High_CS_OE_n <= '0';
      Mem_User_Out.WE_Out_n <= To_X01 ( User_Out.Write_Sel_n );
      Mem_User_Out.WE_OE_n <= '0';
      Mem_User_Out.Xbar_Mode_Out <= User_Out.Xbar_Mode_Out;
      Mem_User_Out.Xbar_Mode_OE_n <= ( others => User_Out.Xbar_Mode_OE_n );
    else
      Mem_User_Out.Addr_Out <= "0" & To_X01 ( User_Out.Shunt_Out(21 downto 4) );
      Mem_User_Out.Addr_OE_n <= "1" & To_X01 ( User_Out.Shunt_OE_n(21 downto 4) );
      Mem_User_Out.Addr_CS_Out_n <= To_X01 ( User_Out.Shunt_Out(3) );
      Mem_User_Out.Addr_CS_OE_n <= To_X01 ( User_Out.Shunt_OE_n(3) );
      Mem_User_Out.Low_CS_Out_n <= To_X01 ( User_Out.Shunt_Out(2) );
      Mem_User_Out.Low_CS_OE_n <= To_X01 ( User_Out.Shunt_OE_n(2) );
      Mem_User_Out.High_CS_Out_n <= To_X01 ( User_Out.Shunt_Out(1) );
      Mem_User_Out.High_CS_OE_n <= To_X01 ( User_Out.Shunt_OE_n(1) );
      Mem_User_Out.WE_Out_n <= To_X01 ( User_Out.Shunt_Out(0) );
      Mem_User_Out.WE_OE_n <= To_X01 ( User_Out.Shunt_OE_n(0) );
      Mem_User_Out.Xbar_Mode_Out <= User_Out.Xbar_Mode_Out;
      Mem_User_Out.Xbar_Mode_OE_n <= ( others => User_Out.Xbar_Mode_OE_n );
    end if;

    v_shunt_out := x"00000000" & To_X01 ( User_Out.Shunt_Out(53 downto 22) );
    v_shunt_oe_n := x"FFFFFFFF" & To_X01 ( User_Out.Shunt_OE_n(53 downto 22) );
    for i in 0 to 3 loop
      if ( Shunt_dd(i) = '0' ) then
        Mem_User_Out.Data_Out((16*i)+15 downto i*16) <= Data_Out_dd((16*i)+15 downto i*16);
        Mem_User_Out.Data_OE_n((16*i)+15 downto i*16) <= 
		( (not Write_dd(i)) & (not Write_dd(i)) & (not Write_dd(i)) & (not Write_dd(i)) 
		& (not Write_dd(i)) & (not Write_dd(i)) & (not Write_dd(i)) & (not Write_dd(i)) 
		& (not Write_dd(i)) & (not Write_dd(i)) & (not Write_dd(i)) & (not Write_dd(i)) 
		& (not Write_dd(i)) & (not Write_dd(i)) & (not Write_dd(i)) & (not Write_dd(i)) );
      else
        Mem_User_Out.Data_Out((16*i)+15 downto i*16) <= v_shunt_out((16*i)+15 downto i*16);
        Mem_User_Out.Data_OE_n((16*i)+15 downto i*16) <= v_shunt_oe_n((16*i)+15 downto i*16);
      end if;
    end loop;

  end process;

  ----------------------------------------------------------------------
  --
  --  Register every signal in the IOBs:
  --
  --    All active high signals use IOB_FDC (async clear)
  --    All active low signals use IOB_FDP (async preset)
  --
  ----------------------------------------------------------------------
  G_Addr : for I in Mem_IO_Out.Addr_Out'range generate
    U_Addr_In : IOB_FDC
      port map
      (
        C   => M_Clk,
        CLR => Global_Reset,
        D   => Mem_IO_In.Addr_In(I),
        Q   => Mem_User_In.Addr_In(I)
      );
    U_Addr_Out : IOB_FDC
      port map
      (
        C   => M_Clk,
        CLR => Global_Reset,
        D   => Mem_User_Out.Addr_Out(I),
        Q   => Mem_IO_Out.Addr_Out(I)
      );
    U_Addr_OE : IOB_FDP
      port map
      (
        C   => M_Clk,
        PRE => Global_Reset,
        D   => Mem_User_Out.Addr_OE_n(I),
        Q   => Mem_IO_Out.Addr_OE_n(I)
      );
  end generate G_Addr;

  G_Data : for I in Mem_IO_Out.Data_Out'range generate
    U_Data_In : IOB_FDC
      port map
      (
        C   => M_Clk,
        CLR => Global_Reset,
        D   => Mem_IO_In.Data_In(I),
        Q   => Mem_User_In.Data_In(I)
      );
    U_Data_Out : IOB_FDC
      port map
      (
        C   => M_Clk,
        CLR => Global_Reset,
        D   => Mem_User_Out.Data_Out(I),
        Q   => Mem_IO_Out.Data_Out(I)
      );
    U_Data_OE : IOB_FDP
      port map
      (
        C   => M_Clk,
        PRE => Global_Reset,
        D   => Mem_User_Out.Data_OE_n(I),
        Q   => Mem_IO_Out.Data_OE_n(I)
      );
  end generate G_Data;

  G_Xbar_Mode : for I in Mem_IO_Out.Xbar_Mode_Out'range generate
    U_Xbar_Mode_In : IOB_FDC
      port map
      (
        C   => M_Clk,
        CLR => Global_Reset,
        D   => Mem_IO_In.Xbar_Mode_In(I),
        Q   => Mem_User_In.Xbar_Mode_In(I)
      );
    U_Xbar_Mode_Out : IOB_FDC
      port map
      (
        C   => M_Clk,
        CLR => Global_Reset,
        D   => Mem_User_Out.Xbar_Mode_Out(I),
        Q   => Mem_IO_Out.Xbar_Mode_Out(I)
      );
    U_Xbar_Mode_OE : IOB_FDP
      port map
      (
        C   => M_Clk,
        PRE => Global_Reset,
        D   => Mem_User_Out.Xbar_Mode_OE_n(I),
        Q   => Mem_IO_Out.Xbar_Mode_OE_n(I)
      );
  end generate G_Xbar_Mode;

  U_Addr_CS_In : IOB_FDP
    port map
    (
      C   => M_Clk,
      PRE => Global_Reset,
      D   => Mem_IO_In.Addr_CS_In_n,
      Q   => Mem_User_In.Addr_CS_In_n
    );

  U_Low_CS_In : IOB_FDP
    port map
    (
      C   => M_Clk,
      PRE => Global_Reset,
      D   => Mem_IO_In.Low_CS_In_n,
      Q   => Mem_User_In.Low_CS_In_n
    );

  U_High_CS_In : IOB_FDP
    port map
    (
      C   => M_Clk,
      PRE => Global_Reset,
      D   => Mem_IO_In.High_CS_In_n,
      Q   => Mem_User_In.High_CS_In_n
    );

  U_WE_In : IOB_FDP
    port map
    (
      C   => M_Clk,
      PRE => Global_Reset,
      D   => Mem_IO_In.WE_In_n,
      Q   => Mem_User_In.WE_In_n
    );

  U_Addr_CS_Out : IOB_FDP
    port map
    (
      C   => M_Clk,
      PRE => Global_Reset,
      D   => Mem_User_Out.Addr_CS_Out_n,
      Q   => Mem_IO_Out.Addr_CS_Out_n
    );

  U_Addr_CS_OE : IOB_FDP
    port map
    (
      C   => M_Clk,
      PRE => Global_Reset,
      D   => Mem_User_Out.Addr_CS_OE_n,
      Q   => Mem_IO_Out.Addr_CS_OE_n
    );

  U_Low_CS_Out : IOB_FDP
    port map
    (
      C   => M_Clk,
      PRE => Global_Reset,
      D   => Mem_User_Out.Low_CS_Out_n,
      Q   => Mem_IO_Out.Low_CS_Out_n
    );

  U_Low_CS_OE : IOB_FDP
    port map
    (
      C   => M_Clk,
      PRE => Global_Reset,
      D   => Mem_User_Out.Low_CS_OE_n,
      Q   => Mem_IO_Out.Low_CS_OE_n
    );

  U_High_CS_Out : IOB_FDP
    port map
    (
      C   => M_Clk,
      PRE => Global_Reset,
      D   => Mem_User_Out.High_CS_Out_n,
      Q   => Mem_IO_Out.High_CS_Out_n
    );

  U_High_CS_OE : IOB_FDP
    port map
    (
      C   => M_Clk,
      PRE => Global_Reset,
      D   => Mem_User_Out.High_CS_OE_n,
      Q   => Mem_IO_Out.High_CS_OE_n
    );

  U_WE_Out : IOB_FDP
    port map
    (
      C   => M_Clk,
      PRE => Global_Reset,
      D   => Mem_User_Out.WE_Out_n,
      Q   => Mem_IO_Out.WE_Out_n
    );

  U_WE_OE : IOB_FDP
    port map
    (
      C   => M_Clk,
      PRE => Global_Reset,
      D   => Mem_User_Out.WE_OE_n,
      Q   => Mem_IO_Out.WE_OE_n
    );

end Standard;