pex_synth.vhd

arm9_fpga2_verilog是一个可以综合的用verilog写的arm9的ip软核

    ARM_Mem_Out.Strobe_n when (ARM_Left_Mem_Mux_Sel = '1') else
    Inactive_Mem_Out.Strobe_n;

  Left_Mem_Out.Write_Sel_n <= 
    Host_Mem_Out.Write_Sel_n when (Host_Left_Mem_Mux_Sel = '1') else
    ARM_Mem_Out.Write_Sel_n when (ARM_Left_Mem_Mux_Sel = '1') else
    Inactive_Mem_Out.Write_Sel_n;

  Right_Mem_Out.Addr <=
    ('0' & Host_Mem_Out.Addr (18 downto 0)) when (Host_Right_Mem_Mux_Sel = '1') else
    ('0' & ARM_Mem_Out.Addr (18 downto 0)) when (ARM_Right_Mem_Mux_Sel = '1') else 
    Inactive_Mem_Out.Addr;
  
  Right_Mem_Out.Data_Out <=
    Host_Mem_Out.Data_Out when (Host_Right_Mem_Mux_Sel = '1') else
    ARM_Mem_Out.Data_Out when (ARM_Right_Mem_Mux_Sel = '1') else
    Inactive_Mem_Out.Data_Out;
  
  Right_Mem_Out.Strobe_n <=
    Host_Mem_Out.Strobe_n when (Host_Right_Mem_Mux_Sel = '1') else
    ARM_Mem_Out.Strobe_n when (ARM_Right_Mem_Mux_Sel = '1') else
    Inactive_Mem_Out.Strobe_n;
  
  Right_Mem_Out.Write_Sel_n <=
    Host_Mem_Out.Write_Sel_n when (Host_Right_Mem_Mux_Sel = '1') else
    ARM_Mem_Out.Write_Sel_n when (ARM_Right_Mem_Mux_Sel = '1') else
    Inactive_Mem_Out.Write_Sel_n;

  Left_Mezz_Out.Addr <=
    ('0' & Host_Mem_Out.Addr(19 downto 1)) when (Host_Left_Mezz_Mux_Sel = '1') else
    ('0' & ARM_Mem_Out.Addr(19 downto 1)) when (ARM_Left_Mezz_Mux_Sel = '1') else
    Inactive_Mem_Out.Addr;

  Left_Mezz_Out.Data_Out <=
    (Host_Mem_Out.Data_Out & Host_Mem_Out.Data_Out) when (Host_Left_Mezz_Mux_Sel = '1') else
    (ARM_Mem_Out.Data_Out & ARM_Mem_Out.Data_Out) when (ARM_Left_Mezz_Mux_Sel = '1') else
    (Inactive_Mem_Out.Data_Out & Inactive_Mem_Out.Data_Out);

  Left_Mezz_Out.Low_Strobe_n <=
    Host_Mem_Out.Strobe_n when (Host_Left_Mezz_Mux_Sel = '1' AND Host_Mem_Out.Addr(0) = '0') else
    ARM_Mem_Out.Strobe_n when (ARM_Left_Mezz_Mux_Sel = '1' AND ARM_Mem_Out.Addr(0) = '0') else
    Inactive_Mem_Out.Strobe_n;

  Left_Mezz_Out.High_Strobe_n <= 
    Host_Mem_Out.Strobe_n when (Host_Left_Mezz_Mux_Sel = '1' AND Host_Mem_Out.Addr(0) = '1') else
    ARM_Mem_Out.Strobe_n when (ARM_Left_Mezz_Mux_Sel = '1' AND ARM_Mem_Out.Addr(0) = '1') else
    Inactive_Mem_Out.Strobe_n;

  Left_Mezz_Out.Write_Sel_n <=
    Host_Mem_Out.Write_Sel_n when (Host_Left_Mezz_Mux_Sel = '1') else
    ARM_Mem_Out.Write_Sel_n when (ARM_Left_Mezz_Mux_Sel = '1') else
    Inactive_Mem_Out.Write_Sel_n;

  Left_Mezz_Out.Xbar_Mode_Out <= 
    "00" when (Host_Left_Mezz1_Sel = '1' OR ARM_Left_Mezz1_Sel = '1') else "01";

  Left_Mezz_Out.Xbar_Mode_OE_n <= '0';
--    '0' when (Host_Left_Mezz_Mux_Sel = '1' OR ARM_Left_Mezz_Mux_Sel = '1') else '1';

  Left_Mezz_Out.Shunt_Out <= (others => '0');
  Left_Mezz_Out.Shunt_OE_n <= (others => '1');

  Right_Mezz_Out.Addr <=
    ('0' & Host_Mem_Out.Addr(19 downto 1)) when (Host_Right_Mezz_Mux_Sel = '1') else
    ('0' & ARM_Mem_Out.Addr(19 downto 1)) when (ARM_Right_Mezz_Mux_Sel = '1') else
    Inactive_Mem_Out.Addr;
                
  Right_Mezz_Out.Data_Out <=
    (Host_Mem_Out.Data_Out & Host_Mem_Out.Data_Out) when (Host_Right_Mezz_Mux_Sel = '1') else
    (ARM_Mem_Out.Data_Out & ARM_Mem_Out.Data_Out) when (ARM_Right_Mezz_Mux_Sel = '1') else
    (Inactive_Mem_Out.Data_Out & Inactive_Mem_Out.Data_Out);
  
  Right_Mezz_Out.Low_Strobe_n <=
    Host_Mem_Out.Strobe_n when (Host_Right_Mezz_Mux_Sel = '1' AND Host_Mem_Out.Addr(0) = '0') else
    ARM_Mem_Out.Strobe_n when (ARM_Right_Mezz_Mux_Sel = '1' AND ARM_Mem_Out.Addr(0) = '0') else
    Inactive_Mem_Out.Strobe_n;
  
  Right_Mezz_Out.High_Strobe_n <=
    Host_Mem_Out.Strobe_n when (Host_Right_Mezz_Mux_Sel = '1' AND Host_Mem_Out.Addr(0) = '1') else
    ARM_Mem_Out.Strobe_n when (ARM_Right_Mezz_Mux_Sel = '1' AND ARM_Mem_Out.Addr(0) = '1') else
    Inactive_Mem_Out.Strobe_n;
  
  Right_Mezz_Out.Write_Sel_n <=
    Host_Mem_Out.Write_Sel_n when (Host_Right_Mezz_Mux_Sel = '1') else
    ARM_Mem_Out.Write_Sel_n when (ARM_Right_Mezz_Mux_Sel = '1') else
    Inactive_Mem_Out.Write_Sel_n;
  
  Right_Mezz_Out.Xbar_Mode_Out <=
    "00" when (Host_Right_Mezz1_Sel = '1' OR ARM_Right_Mezz1_Sel = '1') else "01";
           
  Right_Mezz_Out.Xbar_Mode_OE_n <= '0';
--    '0' when (Host_Right_Mezz_Mux_Sel = '1' OR ARM_Right_Mezz_Mux_Sel = '1') else '1';
  
  Right_Mezz_Out.Shunt_Out <= (others => '0');
  Right_Mezz_Out.Shunt_OE_n <= (others => '1');

  --Use the Bank Selectors to Mux the Input Busses
  Host_Mem_In.Data_In <= 
    Left_Mem_In.Data_In when ( Host_Left_Mem_Mux_Sel = '1' ) else
    Right_Mem_In.Data_In when ( Host_Right_Mem_Mux_Sel = '1' ) else
    Left_Mezz_In.Data_In(31 downto 0) when (Host_Left_Mezz_Mux_Sel = '1' AND Left_Mezz_In.Low_Valid_n = '0') else  
    Left_Mezz_In.Data_In(63 downto 32) when (Host_Left_Mezz_Mux_Sel = '1' AND Left_Mezz_In.High_Valid_n = '0') else
    Right_Mezz_In.Data_In(31 downto 0) when (Host_Right_Mezz_Mux_Sel = '1' AND Right_Mezz_In.Low_Valid_n = '0') else
    Right_Mezz_In.Data_In(63 downto 32) when (Host_Right_Mezz_Mux_Sel = '1' AND Right_Mezz_In.High_Valid_n = '0') else
    Inactive_Mem_In.Data_In;
  
  Host_Mem_In.Data_Valid_n <=
    Left_Mem_In.Data_Valid_n when (Host_Left_Mem_Mux_Sel = '1') else   
    Right_Mem_In.Data_Valid_n when (Host_Right_Mem_Mux_Sel = '1') else 
    (Left_Mezz_In.Low_Valid_n AND Left_Mezz_In.High_Valid_n) when (Host_Left_Mezz_Mux_Sel = '1') else  
    (Right_Mezz_In.Low_Valid_n AND Right_Mezz_In.High_Valid_n) when (Host_Right_Mezz_Mux_Sel = '1') else
    Inactive_Mem_In.Data_Valid_n;

  ARM_Mem_In.Data_In <=
    Left_Mem_In.Data_In when (ARM_Left_Mem_Mux_Sel = '1') else
    Right_Mem_In.Data_In when (ARM_Right_Mem_Mux_Sel = '1') else
    Left_Mezz_In.Data_In(31 downto 0) when (ARM_Left_Mezz_Mux_Sel = '1' AND Left_Mezz_In.Low_Valid_n = '0') else
    Left_Mezz_In.Data_In(63 downto 32) when (ARM_Left_Mezz_Mux_Sel = '1' AND Left_Mezz_In.High_Valid_n = '0') else
    Right_Mezz_In.Data_In(31 downto 0) when (ARM_Right_Mezz_Mux_Sel = '1' AND Right_Mezz_In.Low_Valid_n = '0') else
    Right_Mezz_In.Data_In(63 downto 32) when (ARM_Right_Mezz_Mux_Sel = '1' AND Right_Mezz_In.High_Valid_n = '0') else
    Inactive_Mem_In.Data_In;

  ARM_Mem_In.Data_Valid_n <=
    Left_Mem_In.Data_Valid_n when (ARM_Left_Mem_Mux_Sel = '1') else
    Right_Mem_In.Data_Valid_n when (ARM_Right_Mem_Mux_Sel = '1') else
    (Left_Mezz_In.Low_Valid_n AND Left_Mezz_In.High_Valid_n) when (ARM_Left_Mezz_Mux_Sel = '1') else
    (Right_Mezz_In.Low_Valid_n AND Right_Mezz_In.High_Valid_n) when (ARM_Right_Mezz_Mux_Sel = '1') else
    Inactive_Mem_In.Data_Valid_n;

  ----------------------------------------------------------------------
  -- 
  --  Multiplex the LAD data lines.
  --
  ----------------------------------------------------------------------

  Inactive_LAD_Bus_Out.Data_Out <= ( others => '0' );
  Inactive_LAD_Bus_Out.Int_Req_n <= '1';
  Inactive_LAD_Bus_Out.DMA_Stat <= ( others => '0' );

  LAD_Bus_Out <= 
    Host_Mem_LAD_Bus_Out when ( Host_Mem_LAD_Bus_OE_n = '0' ) else
    Stat_Reg_LAD_Bus_Out when ( Stat_Reg_LAD_Bus_OE_n = '0' ) else
    Inactive_LAD_Bus_Out;
                 

  ----------------------------------------------------------------------
  -- 
  --  Tie the left and right on-board memory strobe signals to the LEDs
  --
  ----------------------------------------------------------------------
  LEDs_Out.Red_n <= not nWAIT;
  LEDs_Out.Green_n <= not ARM_STOP;

  ----------------------------------------------------------------------
  --
  --  Below are all of the standard PE pad interface components. Simply
  --  uncomment the interface(s) that are needed by the PE design.  All
  --  other unused interfaces may remain commented out.  Be sure to
  --  uncomment any signal declarations used by the interface.
  --
  ----------------------------------------------------------------------

  U_Clocks : Clock_Std_IF
    generic map
    (
      M_CLK_DLL_TYPE  => LOW_FREQ,
      P_CLK_DLL_TYPE  => LOW_FREQ,
      U_CLK_DLL_TYPE  => NONE
    )
    port map
    (
      Pads    => Pads.Clocks,
      User_In => Clocks_In
    );

  U_LAD_Bus : LAD_Bus_Std_IF
    port map
    (
      K_Clk         => Clocks_In.K_Clk,
      Global_Reset  => Global_Reset,
      Pads          => Pads.LAD_Bus,
      User_In       => LAD_Bus_In,
      User_Out      => LAD_Bus_Out
    );

  U_LEDs : LED_Std_IF
    port map
    (
      Pads          => Pads.LEDs,
      User_Out      => LEDs_Out
    );

  U_Left_Mem : Mem_Std_IF
    generic map
    (
      INFF_Delay    => NODELAY,
      OBUF_Drive    => SLOW_12mA
    )
    port map
    (
      M_Clk         => Clocks_In.M_Clk,
      Global_Reset  => Global_Reset,
      Pads          => Pads.Left_Mem,
      User_In       => Left_Mem_In,
      User_Out      => Left_Mem_Out
    );

  U_Right_Mem : Mem_Std_IF
    generic map
    (
      INFF_Delay    => NODELAY,
      OBUF_Drive    => SLOW_12mA
    )
    port map
    (
      M_Clk         => Clocks_In.M_Clk,
      Global_Reset  => Global_Reset,
      Pads          => Pads.Right_Mem,
      User_In       => Right_Mem_In,
      User_Out      => Right_Mem_Out
    );

  U_Left_Mezz_Mem : Mezz_Mem_Std_IF
    generic map
    (
      INFF_Delay    => NODELAY,
      OBUF_Drive    => SLOW_12mA
    )
    port map
    (
      M_Clk         => Clocks_In.M_Clk,
      Global_Reset  => Global_Reset,
      Pads          => Pads.Mezz.Left,
      User_In       => Left_Mezz_In,
      User_Out      => Left_Mezz_Out
    );

  U_Right_Mezz_Mem : Mezz_Mem_Std_IF
    generic map
    (
      INFF_Delay    => NODELAY,
      OBUF_Drive    => SLOW_12mA
    )
    port map
    (
      M_Clk         => Clocks_In.M_Clk,
      Global_Reset  => Global_Reset,
      Pads          => Pads.Mezz.Right,
      User_In       => Right_Mezz_In,
      User_Out      => Right_Mezz_Out
    );

--  U_PE0_Bus : PE0_Bus_Std_IF
--    generic map
--    (
--      INFF_Delay    => NODELAY,
--      OBUF_Drive    => FAST_8mA
--    )
--    port map
--    (
--      Clk           => Clocks_In.M_Clk,
--      Global_Reset  => Global_Reset,
--      Pads          => Pads.PE0_Bus,
--      User_In       => PE0_Bus_In,
--      User_Out      => PE0_Bus_Out
--    );
--
--  U_Top_Sys : Systolic_Std_IF
--    generic map
--    (
--      INFF_Delay    => NODELAY,
--      OBUF_Drive    => FAST_8mA
--    )
--    port map
--    (
--      Clk           => Clocks_In.M_Clk,
--      Global_Reset  => Global_Reset,
--      Pads          => Pads.Top_Sys,
--      User_In       => Top_Sys_In,
--      User_Out      => Top_Sys_Out
--    );
--
--  U_Bot_Sys : Systolic_Std_IF
--    generic map
--    (
--      INFF_Delay    => NODELAY,
--      OBUF_Drive    => FAST_8mA
--    )
--    port map
--    (
--      Clk           => Clocks_In.M_Clk,
--      Global_Reset  => Global_Reset,
--      Pads          => Pads.Bot_Sys,
--      User_In       => Bot_Sys_In,
--      User_Out      => Bot_Sys_Out
--    );

  ----------------------------------------------------------------------
  --
  --  Global reset interface : Attach the Reset_Register signal to a
  --  register bit of a LAD bus accessible register.  This reset
  --  mechanism generates a one K_Clk cycle long pulse to the GSR line
  --  of the STARTUP block.  The STARTUP block is also synchronous to
  --  K_Clk.
  --
  ----------------------------------------------------------------------
  U_Reset_Pulse_Gen : One_Shot
    port map
    (
      Clk  => Clocks_In.K_Clk,
      I    => Reset_Register,
      O    => Global_Reset
    );

--   changing from STARTUP_VIRTEX_ALL
--  U_Startup : STARTUP_VIRTEX
--    port map
--    (
--      GSR => Global_Reset,
--      GTS => GND,
--      CLK => Clocks_In.K_Clk
--    );

  ----------------------------------------------------------------------
  --  NOTE :  The following line must remain in all designs
  --          to ensure that all of the PE pads are driven.
  ----------------------------------------------------------------------
  Init_PEX_Pads ( Pads );

end Mem_Copy;