pex_synth.vhd

arm9_fpga2_verilog是一个可以综合的用verilog写的arm9的ip软核

  component LAD_To_Mem_Std_IF is
    port
    (
      Global_Reset      : in    std_logic;
      Clocks_In         : in    Clock_Std_IF_In_Type;
      LAD_Bus_In        : in    LAD_Bus_Std_IF_In_Type;
      LAD_Bus_Out       :   out LAD_Bus_Std_IF_Out_Type;
      LAD_Bus_OE_n      :   out std_logic;
      Mem_Data_In       : in    std_logic_vector (31 downto 0);
      Mem_Data_Valid_n  : in    std_logic;
      Mem_Addr          :   out std_logic_vector (19 downto 0);
      Mem_Data_Out      :   out std_logic_vector (31 downto 0);
      Mem_Strobe_n      :   out std_logic;
      Mem_Write_Sel_n   :   out std_logic
    );
  end component;

  component ARM_To_Mem_Std_IF is
    port
    (
      Global_Reset      : in    std_logic;
      Clocks_In         : in    Clock_Std_IF_In_Type;
      MMD_Data_In       : in    std_logic_vector (31 downto 0);
      MMD_Data_Out      :   out std_logic_vector (31 downto 0);
      MMnWR             : in    std_logic;
      MM_CE             : in    std_logic;
      MM_New_Line       : in    std_logic;
      MMA		      : in 	  std_logic_vector (31 downto 0);
      Mem_Data_In       : in    std_logic_vector (31 downto 0);
      Mem_Data_Valid_n  : in    std_logic;
      Mem_Addr          :   out std_logic_vector (19 downto 0);
      Mem_Data_Out      :   out std_logic_vector (31 downto 0);
      Mem_Strobe_n      :   out std_logic;
      Mem_Write_Sel_n   :   out std_logic
    );
  end component;

  component arm9 is
    port
    (
      GCLK		: in	  std_logic;
      nRESET		: in 	  std_logic;
      nWAIT		:   out   std_logic;
      nFIQ		: in 	  std_logic;
      nIRQ		: in	  std_logic;
      ISYNC		: in	  std_logic;
      MMD_In		: in	  std_logic_vector (31 downto 0);
      MMD_Out		:   out std_logic_vector (31 downto 0);
      MMA		:   out std_logic_vector (31 downto 0);
      MMnWR		:   out std_logic;
      MM_CE             :   out std_logic;
      MM_New_Line       :   out std_logic;
      STOP		:   out std_logic
    );
  end component;

begin

  ----------------------------------------------------------------------
  --   
  --  The P_Reset process is used for the global reset.  When the host
  --  writes to address defined as RESET_BASE the global reset register
  --  will be high for one K_Clk pulse and return low.  
  --
  ----------------------------------------------------------------------  

  K_CLK <= Clocks_In.K_Clk;
  P_Reset : process ( Global_Reset, K_CLK )
  begin
    if ( Global_Reset = '1' ) then
      Reset_Register <= '0';
    elsif ( rising_edge ( K_CLK ) ) then
      if ( LAD_Bus_In.Reg_Strobe_n = '0' ) then
        if ( LAD_Bus_In.Write_Sel_n = '0' ) then
          if ( ( LAD_Bus_In.Addr ( RESET_BASE'range ) and BASE_MASK ) = 
                 RESET_BASE ) then
            Reset_Register <= '1';
          end if;
        end if;
      end if;
    end if;
  end process P_Reset;

  ----------------------------------------------------------------------
  --   
  --  The P_Ctrl process is used for the control register.
  --
  ----------------------------------------------------------------------  

  K_Ctrl : process ( Global_Reset, K_CLK )
  begin
    if ( Global_Reset = '1' ) then

      Host_App_Sel <= '0';

    elsif ( rising_edge ( K_CLK ) ) then
      if ( LAD_Bus_In.Reg_Strobe_n = '0' ) then
        if ( LAD_Bus_In.Write_Sel_n = '0' ) then
          if ( ( LAD_Bus_In.Addr ( CTRL_BASE'range ) and BASE_MASK ) = 
                 CTRL_BASE ) then

            Host_App_Sel <= LAD_Bus_In.Data_In(0);

          end if;
        end if;
      end if;
    end if;
  end process K_Ctrl;

  HostAddr_Reg : process ( Global_Reset, K_CLK )
  begin 
    if ( Global_Reset = '1' ) then
      Host_Mem_Addr <= (others => '0' );

    elsif ( rising_edge ( K_CLK ) ) then
      if ( LAD_Bus_In.Reg_Strobe_n = '0' ) then
	if ( ( LAD_Bus_In.Addr ( MEM_REG_BASE'range ) and BASE_MASK ) =
	       MEM_REG_BASE ) then
          if ( LAD_Bus_In.Write_Sel_n = '0' ) then
            if (LAD_Bus_In.Addr (1 downto 0) = "00") then

              Host_Mem_Addr <= Lad_Bus_In.Data_In(24 downto 0);

            end if; 
          end if;
        end if;
      end if;
    end if;
  end process HostAddr_Reg;

  ----------------------------------------------------------------------
  --
  --  The P_Stat process is used for the status register.
  --
  ----------------------------------------------------------------------

  Stat_Reg_LAD_Bus_Out.Int_Req_n <= '1';
  Stat_Reg_LAD_Bus_Out.DMA_Stat <= ( others => '0' );
  Stat_Reg_LAD_Bus_Out.Data_Out(31 downto 1) <= ( others => '0' );

  P_Stat : process ( Global_Reset, K_CLK )
  begin
    if ( Global_Reset = '1' ) then
      K_Done <= '0';
      Stat_Reg_LAD_Bus_Out.Data_Out(0) <= '0';
      Stat_Reg_LAD_Bus_OE_n <= '1';
    elsif ( rising_edge ( K_CLK ) ) then
      K_Done <= ARM_STOP;
      Stat_Reg_LAD_Bus_OE_n <= '1';
      if ( LAD_Bus_In.Reg_Strobe_n = '0' ) then
        if ( LAD_Bus_In.Write_Sel_n = '1' ) then
          if ( ( LAD_Bus_In.Addr ( STAT_BASE'range ) and BASE_MASK ) =
                 STAT_BASE ) then
            Stat_Reg_LAD_Bus_OE_n <= '0';
            Stat_Reg_LAD_Bus_Out.Data_Out(0) <= K_Done;
          end if;
        end if;
      end if;
    end if;
  end process P_Stat;


  ----------------------------------------------------------------------
  --   
  --  The Host_Mem_Buffer component controls memory access to/from
  --  the memory port from the LAD. 
  --
  ----------------------------------------------------------------------  
  Host_Mem_Buffer : LAD_To_Mem_Std_IF
    port map
    (
      Global_Reset      => Global_Reset,
      Clocks_In         => Clocks_In,
      LAD_Bus_In        => LAD_Bus_In,
      LAD_Bus_Out       => Host_Mem_LAD_Bus_Out,
      LAD_Bus_OE_n      => Host_Mem_LAD_Bus_OE_n,
      Mem_Data_In       => Host_Mem_In.Data_In,
      Mem_Data_Valid_n  => Host_Mem_In.Data_Valid_n,
      Mem_Addr          => Host_Mem_Out.Addr,
      Mem_Data_Out      => Host_Mem_Out.Data_Out,
      Mem_Strobe_n      => Host_Mem_Out.Strobe_n,
      Mem_Write_Sel_n   => Host_Mem_Out.Write_Sel_n
    );

  ----------------------------------------------------------------------
  --
  --  The ARM_Mem_Buffer component controls memory access to/from
  --  the memory port from the ARM CPU.
  --
  ----------------------------------------------------------------------
  ARM_Mem_Buffer : ARM_To_Mem_Std_IF
    port map
    (
      Global_Reset      => Global_Reset,
      Clocks_In         => Clocks_In,
      MMD_Data_In       => MMD_Data_In,
      MMD_Data_Out      => MMD_Data_Out,
      MMnWR             => MMnWR,
      MM_CE             => MM_CE,
      MM_New_Line       => MM_New_Line,
      MMA		=> MMA,
      Mem_Data_In       => ARM_Mem_In.Data_In,
      Mem_Data_Valid_n  => ARM_Mem_In.Data_Valid_n,
      Mem_Addr          => ARM_Mem_Out.Addr,
      Mem_Data_Out      => ARM_Mem_Out.Data_Out,
      Mem_Strobe_n      => ARM_Mem_Out.Strobe_n,
      Mem_Write_Sel_n   => ARM_Mem_Out.Write_Sel_n
    );

  ----------------------------------------------------------------------
  --
  --  The ARM Processor
  --  
  ----------------------------------------------------------------------

  nRESET <= not Global_Reset;
  nFIQ <= '1';
  nIRQ <= '1';
  ISYNC <= '1';

  ARM : arm9
    port map
    (
      GCLK              => P_CLK,
      nRESET            => nRESET,
      nWAIT		=> nWAIT,
      nFIQ              => nFIQ,
      nIRQ              => nIRQ,
      ISYNC             => ISYNC,
      MMD_In            => MMD_Data_Out,
      MMD_Out           => MMD_Data_In,
      MMA               => MMA,
      MMnWR             => MMnWR,
      MM_CE             => MM_CE,
      MM_New_Line       => MM_New_Line,
      STOP		=> ARM_STOP
    );

  ----------------------------------------------------------------------
  --
  -- ARM Control Register
  --
  ----------------------------------------------------------------------

  P_CLK <= Clocks_In.U_Clk;
  P_Ctrl : process ( Global_Reset, P_CLK )
  begin
    if ( Global_Reset = '1' ) then
      ARM_Mem_Addr <= ( others => '0' ); 
    elsif ( rising_edge ( P_CLK ) ) then
      if (MM_New_Line = '1') then
        ARM_Mem_Addr <= MMA;
      end if;
    end if;
  end process P_Ctrl;
      
  ----------------------------------------------------------------------
  -- 
  --  Multiplex the memory buffer lines.
  --
  ----------------------------------------------------------------------

  --Setup Inactive Busses to avoid excessive loads on busses in use
  Inactive_Mem_In.Data_In <= ( others => '0');
  Inactive_Mem_In.Data_Valid_n <= '0';
  Inactive_Mem_Out.Data_Out <= ( others => '0');
  Inactive_Mem_Out.Addr <= ( others => '0');
  Inactive_Mem_Out.Strobe_n <= '1';
  Inactive_Mem_Out.Write_Sel_n <= '1';

  --Decode the Memory Bank Needed and who has Access
  Host_Left_Mem_Mux_Sel <= '1' when ((("00000" & Host_Mem_Addr(24 downto 19)) = 
		LEFT_MEM_TAG) AND (Host_App_Sel = '1')) else '0';
  
  Host_Right_Mem_Mux_Sel <= '1' when ((("00000" & Host_Mem_Addr(24 downto 19)) = 
		RIGHT_MEM_TAG) AND (Host_App_Sel = '1')) else '0';

  Host_Left_Mezz0_Sel <= '1' when ((("00000" & Host_Mem_Addr(24 downto 20)) =
		LEFT_MEZZ0_TAG) AND (Host_App_Sel = '1')) else '0';

  Host_Left_Mezz1_Sel <= '1' when ((("00000" & Host_Mem_Addr(24 downto 20)) =
		LEFT_MEZZ1_TAG) AND (Host_App_Sel = '1')) else '0';

  Host_Left_Mezz_Mux_Sel <= '1' when ((Host_Left_Mezz0_Sel = '1') OR
                (Host_Left_Mezz1_Sel = '1')) else '0';

  Host_Right_Mezz0_Sel <= '1' when ((("00000" & Host_Mem_Addr(24 downto 20)) =
		RIGHT_MEZZ0_TAG) AND (Host_App_Sel = '1')) else '0';

  Host_Right_Mezz1_Sel <= '1' when ((("00000" & Host_Mem_Addr(24 downto 20)) =
                RIGHT_MEZZ1_TAG) AND (Host_App_Sel = '1')) else '0';

  Host_Right_Mezz_Mux_Sel <= '1' when ((Host_Right_Mezz0_Sel = '1') OR
                (Host_Right_Mezz1_Sel = '1')) else '0';

  ARM_Left_Mem_Mux_Sel <= '1' when ((ARM_Mem_Addr(31 downto 21) = 
		LEFT_MEM_TAG) AND (Host_App_Sel = '0')) else '0';

  ARM_Right_Mem_Mux_Sel <= '1' when ((ARM_Mem_Addr(31 downto 21) = 
		RIGHT_MEM_TAG) AND (Host_App_Sel = '0')) else '0';

  ARM_Left_Mezz0_Sel <= '1' when ((ARM_Mem_Addr(31 downto 22) =
                LEFT_MEZZ0_TAG) AND (Host_App_Sel = '0')) else '0';

  ARM_Left_Mezz1_Sel <= '1' when ((ARM_Mem_Addr(31 downto 22) =
                LEFT_MEZZ1_TAG) AND (Host_App_Sel = '0')) else '0';

  ARM_Left_Mezz_Mux_Sel <= '1' when ((ARM_Left_Mezz0_Sel = '1') OR
		(ARM_Left_Mezz1_Sel = '1')) else '0';

  ARM_Right_Mezz0_Sel <= '1' when ((ARM_Mem_Addr(31 downto 22) =
                RIGHT_MEZZ0_TAG) AND (Host_App_Sel = '0')) else '0';
  
  ARM_Right_Mezz1_Sel <= '1' when ((ARM_Mem_Addr(31 downto 22) =
                RIGHT_MEZZ1_TAG) AND (Host_App_Sel = '0')) else '0';

  ARM_Right_Mezz_Mux_Sel <= '1' when ((ARM_Right_Mezz0_Sel = '1') OR
                (ARM_Right_Mezz1_Sel = '1')) else '0';


  --Use the Bank Selectors to Mux the Output Busses
  Left_Mem_Out.Addr <= 
    ('0' & Host_Mem_Out.Addr (18 downto 0)) when ( Host_Left_Mem_Mux_Sel = '1')	else
    ('0' & ARM_Mem_Out.Addr (18 downto 0)) when ( ARM_Left_Mem_Mux_Sel = '1') else
    Inactive_Mem_Out.Addr;

  Left_Mem_Out.Data_Out <= 
    Host_Mem_Out.Data_Out when (Host_Left_Mem_Mux_Sel = '1') else
    ARM_Mem_Out.Data_Out when ( ARM_Left_Mem_Mux_Sel = '1') else
    Inactive_Mem_Out.Data_Out;

  Left_Mem_Out.Strobe_n <= 
    Host_Mem_Out.Strobe_n when (Host_Left_Mem_Mux_Sel = '1') else