📄 divider_stg_1.rpt
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# !divisor3 & !_LC4_C21 & _LC5_C21
# !_LC1_C21 & !_LC4_C21 & _LC5_C21;
-- Node name is ':392'
-- Equation name is '_LC2_C14', type is buried
!_LC2_C14 = _LC2_C14~NOT;
_LC2_C14~NOT = LCELL( _EQ076);
_EQ076 = _LC1_C14 & !_LC3_C21 & !_LC8_C21
# !_LC1_C14 & _LC3_C21 & !_LC8_C21
# _LC1_C1 & !_LC8_C21
# !_LC1_C1 & _LC1_C14 & !_LC3_C21
# !_LC1_C1 & !_LC1_C14 & _LC3_C21;
-- Node name is ':393'
-- Equation name is '_LC2_C21', type is buried
_LC2_C21 = LCELL( _EQ077);
_EQ077 = !_LC1_C1 & _LC6_C21
# divisor3 & _LC6_C21
# !divisor3 & _LC1_C1 & _LC7_C21;
-- Node name is ':394'
-- Equation name is '_LC4_C20', type is buried
_LC4_C20 = LCELL( _EQ078);
_EQ078 = !_LC1_C1 & _LC3_C20
# divisor3 & _LC3_C20
# !divisor3 & _LC1_C1 & _LC2_C22;
-- Node name is ':395'
-- Equation name is '_LC5_C16', type is buried
_LC5_C16 = LCELL( _EQ079);
_EQ079 = !divisor3 & _LC1_C1 & _LC1_C16
# divisor3 & _LC2_C16
# !_LC1_C1 & _LC2_C16;
-- Node name is ':409'
-- Equation name is '_LC3_C16', type is buried
_LC3_C16 = LCELL( _EQ080);
_EQ080 = !divisor3 & _LC1_C1 & !_LC8_C21;
-- Node name is ':422'
-- Equation name is '_LC3_C24', type is buried
_LC3_C24 = LCELL( _EQ081);
_EQ081 = divisor2 & _LC3_C16
# divisor3 & !_LC3_C16;
-- Node name is ':423'
-- Equation name is '_LC5_C23', type is buried
_LC5_C23 = LCELL( _EQ082);
_EQ082 = divisor1 & _LC3_C16
# divisor2 & !_LC3_C16;
-- Node name is ':424'
-- Equation name is '_LC1_C23', type is buried
_LC1_C23 = LCELL( _EQ083);
_EQ083 = divisor0 & _LC3_C16
# divisor1 & !_LC3_C16;
-- Node name is ':476'
-- Equation name is '_LC2_C15', type is buried
_LC2_C15 = LCELL( _EQ084);
_EQ084 = divisor3
# _LC8_C21;
-- Node name is ':499'
-- Equation name is '_LC1_C2', type is buried
!_LC1_C2 = _LC1_C2~NOT;
_LC1_C2~NOT = LCELL( GND);
-- Node name is ':505'
-- Equation name is '_LC3_C11', type is buried
_LC3_C11 = LCELL( _EQ085);
_EQ085 = !_LC1_C17
# !_LC1_C2 & _LC5_C11;
-- Node name is ':506'
-- Equation name is '_LC6_C14', type is buried
_LC6_C14 = LCELL( _EQ086);
_EQ086 = !_LC1_C17 & !_LC2_C14
# !_LC1_C2 & _LC4_C14;
-- Node name is ':537'
-- Equation name is '_LC5_C14', type is buried
_LC5_C14 = LCELL( _EQ087);
_EQ087 = _LC2_C1 & !_LC2_C14
# _LC1_C17 & _LC2_C1;
-- Node name is ':540'
-- Equation name is '_LC7_C11', type is buried
!_LC7_C11 = _LC7_C11~NOT;
_LC7_C11~NOT = LCELL( _EQ088);
_EQ088 = !_LC1_C1 & !_LC2_C1 & !_LC7_C1 & !_LC8_C1;
-- Node name is '~545~1'
-- Equation name is '~545~1', location is LC6_C11, type is buried.
-- synthesized logic cell
_LC6_C11 = LCELL( _EQ089);
_EQ089 = !_LC1_C2 & _LC8_C1 & _LC8_C11
# !_LC1_C2 & _LC2_C1 & _LC8_C11;
-- Node name is ':545'
-- Equation name is '_LC8_C11', type is buried
_LC8_C11 = LCELL( _EQ090);
_EQ090 = _LC6_C11
# !_LC7_C11
# _LC6_C1 & _LC6_C23;
-- Node name is '~546~1'
-- Equation name is '~546~1', location is LC4_C11, type is buried.
-- synthesized logic cell
_LC4_C11 = LCELL( _EQ091);
_EQ091 = _LC3_C11 & _LC8_C1
# _LC1_C1 & _LC2_C15;
-- Node name is ':546'
-- Equation name is '_LC5_C11', type is buried
_LC5_C11 = LCELL( _EQ092);
_EQ092 = _LC2_C1 & _LC5_C11
# _LC1_C2 & _LC2_C1
# _LC4_C11;
-- Node name is '~547~1'
-- Equation name is '~547~1', location is LC7_C14, type is buried.
-- synthesized logic cell
_LC7_C14 = LCELL( _EQ093);
_EQ093 = divisor3 & _LC1_C1
# _LC1_C1 & !_LC8_C21
# _LC2_C7;
-- Node name is ':547'
-- Equation name is '_LC4_C14', type is buried
_LC4_C14 = LCELL( _EQ094);
_EQ094 = _LC5_C14
# _LC6_C14 & _LC8_C1
# _LC7_C14;
-- Node name is ':564'
-- Equation name is '_LC2_C7', type is buried
_LC2_C7 = LCELL( _EQ095);
_EQ095 = _LC6_C1 & !_LC6_C23 & word17;
-- Node name is ':643'
-- Equation name is '_LC8_C13', type is buried
_LC8_C13 = LCELL( _EQ096);
_EQ096 = _LC5_C13 & !_LC8_C14
# _LC3_C14 & !_LC3_C16 & !_LC8_C14
# _LC3_C16 & _LC5_C13;
-- Node name is ':660'
-- Equation name is '_LC4_C7', type is buried
_LC4_C7 = DFFE( _EQ097, GLOBAL( clock), GLOBAL(!reset), VCC, VCC);
_EQ097 = !_LC2_C7 & !_LC2_C19 & _LC6_C7
# !_LC2_C7 & _LC2_C19 & _LC4_C7;
-- Node name is ':661'
-- Equation name is '_LC6_C7', type is buried
_LC6_C7 = DFFE( _EQ098, GLOBAL( clock), GLOBAL(!reset), VCC, VCC);
_EQ098 = _LC1_C7 & !_LC2_C7 & !_LC2_C19
# !_LC2_C7 & _LC2_C19 & _LC6_C7;
-- Node name is ':662'
-- Equation name is '_LC1_C7', type is buried
_LC1_C7 = DFFE( _EQ099, GLOBAL( clock), GLOBAL(!reset), VCC, VCC);
_EQ099 = !_LC2_C7 & !_LC2_C19 & _LC3_C7
# _LC1_C7 & !_LC2_C7 & _LC2_C19;
-- Node name is ':663'
-- Equation name is '_LC3_C7', type is buried
_LC3_C7 = DFFE( _EQ100, GLOBAL( clock), GLOBAL(!reset), VCC, VCC);
_EQ100 = !_LC2_C7 & !_LC2_C19 & _LC7_C7
# !_LC2_C7 & _LC2_C19 & _LC3_C7;
-- Node name is ':664'
-- Equation name is '_LC7_C7', type is buried
_LC7_C7 = DFFE( _EQ101, GLOBAL( clock), GLOBAL(!reset), VCC, VCC);
_EQ101 = !_LC2_C7 & !_LC2_C19 & _LC5_C7
# !_LC2_C7 & _LC2_C19 & _LC7_C7;
-- Node name is ':665'
-- Equation name is '_LC5_C7', type is buried
_LC5_C7 = DFFE( _EQ102, GLOBAL( clock), GLOBAL(!reset), VCC, VCC);
_EQ102 = !_LC2_C7 & !_LC2_C19 & _LC7_C13
# !_LC2_C7 & _LC2_C19 & _LC5_C7;
-- Node name is ':666'
-- Equation name is '_LC7_C13', type is buried
_LC7_C13 = DFFE( _EQ103, GLOBAL( clock), GLOBAL(!reset), VCC, VCC);
_EQ103 = !_LC2_C7 & !_LC2_C19 & _LC5_C13
# !_LC2_C7 & _LC2_C19 & _LC7_C13;
-- Node name is ':667'
-- Equation name is '_LC5_C13', type is buried
_LC5_C13 = DFFE( _EQ104, GLOBAL( clock), GLOBAL(!reset), VCC, VCC);
_EQ104 = !_LC2_C7 & _LC8_C13;
-- Node name is ':668'
-- Equation name is '_LC8_C22', type is buried
_LC8_C22 = LCELL( _EQ105);
_EQ105 = dividend7 & _LC7_C22
# _LC7_C22 & !num_Shift_divisor3
# dividend7 & !num_Shift_divisor3;
-- Node name is ':673'
-- Equation name is '_LC7_C22', type is buried
_LC7_C22 = LCELL( _EQ106);
_EQ106 = dividend6 & _LC6_C22
# _LC6_C22 & !num_Shift_divisor2
# dividend6 & !num_Shift_divisor2;
-- Node name is ':678'
-- Equation name is '_LC6_C22', type is buried
_LC6_C22 = LCELL( _EQ107);
_EQ107 = dividend5 & !num_Shift_divisor1
# dividend4 & dividend5 & !num_Shift_divisor0
# dividend4 & !num_Shift_divisor0 & !num_Shift_divisor1;
-- Node name is ':691'
-- Equation name is '_LC3_C1', type is buried
_LC3_C1 = LCELL( _EQ108);
_EQ108 = !reset & !state0 & !state1 & !state2;
-- Node name is ':693'
-- Equation name is '_LC4_C1', type is buried
_LC4_C1 = LCELL( _EQ109);
_EQ109 = !state0 & !state1 & state2;
Project Information d:\verilog hdl\divider_stg_1\divider_stg_1.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
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