divider_stg_1.rpt

是一個用verilog寫成的加法器電路,可把七個元件加起來

-- Node name is '|lpm_add_sub:705|addcore:adder|:67' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_C20', type is buried 
!_LC2_C20 = _LC2_C20~NOT;
_LC2_C20~NOT = LCELL( _EQ038);
  _EQ038 = !_LC2_C23
         #  dividend6 &  divisor2 &  _LC7_C23
         # !dividend6 & !divisor2 &  _LC7_C23
         #  dividend6 & !divisor2 & !_LC7_C23
         # !dividend6 &  divisor2 & !_LC7_C23;

-- Node name is '|lpm_add_sub:705|addcore:adder|:71' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_C21', type is buried 
!_LC3_C21 = _LC3_C21~NOT;
_LC3_C21~NOT = LCELL( _EQ039);
  _EQ039 = !_LC2_C20
         #  dividend7 & !divisor3 & !_LC8_C20
         #  dividend7 &  divisor3 &  _LC8_C20
         # !dividend7 & !divisor3 &  _LC8_C20
         # !dividend7 &  divisor3 & !_LC8_C20;

-- Node name is '|lpm_add_sub:705|addcore:adder|:83' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC2_C16', type is buried 
_LC2_C16 = LCELL( _EQ040);
  _EQ040 = !dividend4 &  dividend5 &  divisor0 &  divisor1
         # !dividend4 & !dividend5 &  divisor0 & !divisor1
         #  dividend4 &  dividend5 & !divisor1
         #  dividend4 & !dividend5 &  divisor1
         #  dividend5 & !divisor0 & !divisor1
         # !dividend5 & !divisor0 &  divisor1;

-- Node name is '|lpm_add_sub:705|addcore:adder|:84' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC3_C20', type is buried 
_LC3_C20 = LCELL( _EQ041);
  _EQ041 =  dividend6 &  divisor2 & !_LC2_C23 & !_LC7_C23
         # !dividend6 & !divisor2 & !_LC2_C23 & !_LC7_C23
         #  dividend6 & !divisor2 & !_LC2_C23 &  _LC7_C23
         # !dividend6 &  divisor2 & !_LC2_C23 &  _LC7_C23
         #  dividend6 &  divisor2 &  _LC2_C23 &  _LC7_C23
         # !dividend6 & !divisor2 &  _LC2_C23 &  _LC7_C23
         #  dividend6 & !divisor2 &  _LC2_C23 & !_LC7_C23
         # !dividend6 &  divisor2 &  _LC2_C23 & !_LC7_C23;

-- Node name is '|lpm_add_sub:705|addcore:adder|:85' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC6_C21', type is buried 
_LC6_C21 = LCELL( _EQ042);
  _EQ042 =  dividend7 & !divisor3 & !_LC2_C20 &  _LC8_C20
         #  dividend7 &  divisor3 & !_LC2_C20 & !_LC8_C20
         # !dividend7 & !divisor3 & !_LC2_C20 & !_LC8_C20
         # !dividend7 &  divisor3 & !_LC2_C20 &  _LC8_C20
         #  dividend7 & !divisor3 &  _LC2_C20 & !_LC8_C20
         #  dividend7 &  divisor3 &  _LC2_C20 &  _LC8_C20
         # !dividend7 & !divisor3 &  _LC2_C20 &  _LC8_C20
         # !dividend7 &  divisor3 &  _LC2_C20 & !_LC8_C20;

-- Node name is '|lpm_add_sub:705|addcore:adder|:86' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC1_C21', type is buried 
_LC1_C21 = LCELL( _EQ043);
  _EQ043 =  dividend7 &  dividend8 & !_LC3_C21 &  _LC8_C20
         # !dividend7 & !dividend8 & !_LC3_C21
         # !dividend8 & !_LC3_C21 & !_LC8_C20
         # !dividend7 &  dividend8 &  _LC3_C21
         #  dividend8 &  _LC3_C21 & !_LC8_C20
         #  dividend7 & !dividend8 &  _LC3_C21 &  _LC8_C20;

-- Node name is '|lpm_add_sub:707|addcore:adder|~86~1' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC1_C14', type is buried 
-- synthesized logic cell 
_LC1_C14 = LCELL( _EQ044);
  _EQ044 = !dividend7 &  dividend8 &  divisor3
         # !dividend7 &  dividend8 & !_LC8_C20
         #  dividend8 &  divisor3 & !_LC8_C20
         #  dividend7 & !dividend8 &  _LC8_C20
         # !dividend8 & !divisor3 &  _LC8_C20
         #  dividend7 & !dividend8 & !divisor3;

-- Node name is ':34' 
-- Equation name is '_LC7_C1', type is buried 
!_LC7_C1 = _LC7_C1~NOT;
_LC7_C1~NOT = LCELL( _EQ045);
  _EQ045 =  state2
         #  state1
         #  state0;

-- Node name is ':46' 
-- Equation name is '_LC6_C23', type is buried 
!_LC6_C23 = _LC6_C23~NOT;
_LC6_C23~NOT = LCELL( _EQ046);
  _EQ046 =  word20
         #  word21
         #  word23
         #  word22;

-- Node name is '~80~1' 
-- Equation name is '~80~1', location is LC6_C1, type is buried.
-- synthesized logic cell 
_LC6_C1  = LCELL( _EQ047);
  _EQ047 =  start & !state0 & !state1 & !state2;

-- Node name is ':83' 
-- Equation name is '_LC1_C1', type is buried 
_LC1_C1  = LCELL( _EQ048);
  _EQ048 =  state0 & !state1 & !state2;

-- Node name is ':114' 
-- Equation name is '_LC8_C1', type is buried 
!_LC8_C1 = _LC8_C1~NOT;
_LC8_C1~NOT = LCELL( _EQ049);
  _EQ049 =  state2
         # !state1
         #  state0;

-- Node name is ':129' 
-- Equation name is '_LC5_C17', type is buried 
_LC5_C17 = LCELL( _EQ050);
  _EQ050 = !num_Shift_dividend2 &  num_Shift_dividend3
         # !_LC4_C17 &  num_Shift_dividend3
         #  _LC4_C17 &  _LC8_C14 &  num_Shift_dividend2 & 
             !num_Shift_dividend3
         # !_LC8_C14 &  num_Shift_dividend3;

-- Node name is '~185~1' 
-- Equation name is '~185~1', location is LC3_C17, type is buried.
-- synthesized logic cell 
_LC3_C17 = LCELL( _EQ051);
  _EQ051 =  num_Shift_dividend2 &  num_Shift_dividend3 & !num_Shift_divisor2 & 
              num_Shift_divisor3
         # !num_Shift_dividend2 &  num_Shift_dividend3 &  num_Shift_divisor2 & 
             !num_Shift_divisor3
         #  num_Shift_dividend2 & !num_Shift_dividend3 & !num_Shift_divisor2 & 
             !num_Shift_divisor3;

-- Node name is ':185' 
-- Equation name is '_LC1_C17', type is buried 
_LC1_C17 = LCELL( _EQ052);
  _EQ052 =  _LC2_C17 &  _LC3_C17 &  num_Shift_dividend1 &  num_Shift_divisor1
         #  _LC2_C17 &  _LC3_C17 & !num_Shift_dividend1 & !num_Shift_divisor1;

-- Node name is ':186' 
-- Equation name is '_LC2_C17', type is buried 
!_LC2_C17 = _LC2_C17~NOT;
_LC2_C17~NOT = LCELL( _EQ053);
  _EQ053 = !num_Shift_dividend0 &  num_Shift_divisor0
         #  num_Shift_dividend0 & !num_Shift_divisor0;

-- Node name is ':200' 
-- Equation name is '_LC2_C1', type is buried 
!_LC2_C1 = _LC2_C1~NOT;
_LC2_C1~NOT = LCELL( _EQ054);
  _EQ054 = !state1
         #  state2
         # !state0;

-- Node name is ':215' 
-- Equation name is '_LC8_C14', type is buried 
!_LC8_C14 = _LC8_C14~NOT;
_LC8_C14~NOT = LCELL( _EQ055);
  _EQ055 = !_LC2_C14
         #  _LC1_C17 & !_LC2_C1
         # !_LC1_C17 & !_LC8_C1
         # !_LC2_C1 & !_LC8_C1;

-- Node name is ':250' 
-- Equation name is '_LC3_C14', type is buried 
!_LC3_C14 = _LC3_C14~NOT;
_LC3_C14~NOT = LCELL( _EQ056);
  _EQ056 =  _LC2_C14
         # !_LC1_C17 & !_LC2_C1
         # !_LC2_C1 & !_LC8_C1;

-- Node name is ':271' 
-- Equation name is '_LC4_C13', type is buried 
_LC4_C13 = LCELL( _EQ057);
  _EQ057 =  _LC2_C21 &  _LC3_C14
         #  dividend7 & !_LC3_C14;

-- Node name is ':272' 
-- Equation name is '_LC5_C20', type is buried 
_LC5_C20 = LCELL( _EQ058);
  _EQ058 =  _LC3_C14 &  _LC4_C20
         #  dividend6 & !_LC3_C14;

-- Node name is ':273' 
-- Equation name is '_LC6_C16', type is buried 
_LC6_C16 = LCELL( _EQ059);
  _EQ059 =  _LC3_C14 &  _LC5_C16
         #  dividend5 & !_LC3_C14;

-- Node name is ':289' 
-- Equation name is '_LC6_C13', type is buried 
_LC6_C13 = LCELL( _EQ060);
  _EQ060 =  _LC4_C13 & !_LC8_C14
         #  dividend6 &  _LC8_C14;

-- Node name is ':290' 
-- Equation name is '_LC6_C20', type is buried 
_LC6_C20 = LCELL( _EQ061);
  _EQ061 =  _LC5_C20 & !_LC8_C14
         #  dividend5 &  _LC8_C14;

-- Node name is ':291' 
-- Equation name is '_LC7_C16', type is buried 
_LC7_C16 = LCELL( _EQ062);
  _EQ062 =  _LC6_C16 & !_LC8_C14
         #  dividend4 &  _LC8_C14;

-- Node name is ':318' 
-- Equation name is '_LC7_C20', type is buried 
_LC7_C20 = LCELL( _EQ063);
  _EQ063 = !_LC3_C16 &  _LC6_C20
         #  dividend6 &  _LC3_C16;

-- Node name is ':319' 
-- Equation name is '_LC8_C16', type is buried 
_LC8_C16 = LCELL( _EQ064);
  _EQ064 = !_LC3_C16 &  _LC7_C16
         #  dividend5 &  _LC3_C16;

-- Node name is '~325~1' 
-- Equation name is '~325~1', location is LC3_C13, type is buried.
-- synthesized logic cell 
_LC3_C13 = LCELL( _EQ065);
  _EQ065 =  dividend8 & !_LC3_C14 & !_LC8_C14
         #  dividend8 &  _LC3_C16;

-- Node name is '~338~1' 
-- Equation name is '~338~1', location is LC4_C18, type is buried.
-- synthesized logic cell 
!_LC4_C18 = _LC4_C18~NOT;
_LC4_C18~NOT = LCELL( _EQ066);
  _EQ066 =  divisor3 &  _LC3_C14
         # !_LC1_C1 &  _LC3_C14;

-- Node name is '~338~2' 
-- Equation name is '~338~2', location is LC6_C18, type is buried.
-- synthesized logic cell 
_LC6_C18 = LCELL( _EQ067);
  _EQ067 = !_LC4_C18 & !_LC5_C18 & !_LC8_C14
         #  dividend3 &  _LC8_C14;

-- Node name is '~338~3' 
-- Equation name is '~338~3', location is LC7_C18, type is buried.
-- synthesized logic cell 
_LC7_C18 = LCELL( _EQ068);
  _EQ068 = !divisor3 &  _LC1_C1 & !_LC8_C14
         # !_LC3_C14 & !_LC8_C14;

-- Node name is '~338~4' 
-- Equation name is '~338~4', location is LC8_C18, type is buried.
-- synthesized logic cell 
_LC8_C18 = LCELL( _EQ069);
  _EQ069 = !_LC3_C16 &  _LC6_C18
         #  dividend4 &  _LC7_C18
         #  dividend4 &  _LC3_C16;

-- Node name is '~339~1' 
-- Equation name is '~339~1', location is LC1_C18, type is buried.
-- synthesized logic cell 
_LC1_C18 = LCELL( _EQ070);
  _EQ070 =  dividend2 & !_LC2_C19
         #  dividend3 &  _LC2_C19;

-- Node name is '~340~1' 
-- Equation name is '~340~1', location is LC8_C19, type is buried.
-- synthesized logic cell 
_LC8_C19 = LCELL( _EQ071);
  _EQ071 =  dividend1 & !_LC2_C19
         #  dividend2 &  _LC2_C19;

-- Node name is '~341~1' 
-- Equation name is '~341~1', location is LC2_C19, type is buried.
-- synthesized logic cell 
_LC2_C19 = LCELL( _EQ072);
  _EQ072 =  _LC3_C16
         # !_LC8_C14;

-- Node name is '~341~2' 
-- Equation name is '~341~2', location is LC6_C19, type is buried.
-- synthesized logic cell 
_LC6_C19 = LCELL( _EQ073);
  _EQ073 =  dividend0 & !_LC2_C19
         #  dividend1 &  _LC2_C19;

-- Node name is '~342~1' 
-- Equation name is '~342~1', location is LC1_C19, type is buried.
-- synthesized logic cell 
_LC1_C19 = LCELL( _EQ074);
  _EQ074 = !_LC8_C14
         #  _LC3_C16;

-- Node name is ':372' 
-- Equation name is '_LC8_C21', type is buried 
!_LC8_C21 = _LC8_C21~NOT;
_LC8_C21~NOT = LCELL( _EQ075);
  _EQ075 =  divisor3 & !_LC1_C21
         # !divisor3 &  _LC4_C21 & !_LC5_C21
         # !_LC1_C21 &  _LC4_C21 & !_LC5_C21