📄 divider_stg_1.rpt
字号:
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
11 - - - 01 OUTPUT 0 1 0 0 error
59 - - C -- OUTPUT 0 1 0 0 quotient0
58 - - C -- OUTPUT 0 1 0 0 quotient1
18 - - A -- OUTPUT 0 1 0 0 quotient2
30 - - C -- OUTPUT 0 1 0 0 quotient3
28 - - C -- OUTPUT 0 1 0 0 quotient4
27 - - C -- OUTPUT 0 1 0 0 quotient5
36 - - - 07 OUTPUT 0 1 0 0 quotient6
60 - - C -- OUTPUT 0 1 0 0 quotient7
10 - - - 01 OUTPUT 0 1 0 0 ready
29 - - C -- OUTPUT 0 1 0 0 remainder0
69 - - A -- OUTPUT 0 0 0 0 remainder1
7 - - - 03 OUTPUT 0 0 0 0 remainder2
65 - - B -- OUTPUT 0 0 0 0 remainder3
79 - - - 24 OUTPUT 0 0 0 0 remainder4
23 - - B -- OUTPUT 0 0 0 0 remainder5
71 - - A -- OUTPUT 0 0 0 0 remainder6
37 - - - 09 OUTPUT 0 0 0 0 remainder7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\verilog hdl\divider_stg_1\divider_stg_1.rpt
divider_stg_1
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - C 17 AND2 0 2 0 2 |lpm_add_sub:699|addcore:adder|:55
- 5 - C 24 AND2 0 2 0 1 |lpm_add_sub:700|addcore:adder|:55
- 8 - C 24 AND2 0 3 0 1 |lpm_add_sub:700|addcore:adder|:59
- 1 - C 22 OR2 0 3 0 2 |lpm_add_sub:702|addcore:adder|pcarry1
- 3 - C 22 OR2 0 3 0 3 |lpm_add_sub:702|addcore:adder|pcarry2
- 5 - C 22 OR2 0 3 0 2 |lpm_add_sub:702|addcore:adder|:89
- 4 - C 22 OR2 ! 0 4 0 2 |lpm_add_sub:703|addcore:adder|:71
- 5 - C 21 OR2 ! 0 4 0 1 |lpm_add_sub:703|addcore:adder|:75
- 1 - C 16 OR2 0 2 0 1 |lpm_add_sub:703|addcore:adder|:91
- 2 - C 22 OR2 0 4 0 1 |lpm_add_sub:703|addcore:adder|:92
- 7 - C 21 OR2 0 4 0 1 |lpm_add_sub:703|addcore:adder|:93
- 4 - C 21 OR2 s 0 4 0 1 |lpm_add_sub:703|addcore:adder|~94~1
- 7 - C 23 OR2 0 4 0 3 |lpm_add_sub:704|addcore:adder|pcarry1
- 8 - C 20 OR2 0 3 0 4 |lpm_add_sub:704|addcore:adder|pcarry2
- 5 - C 18 OR2 0 2 0 1 |lpm_add_sub:704|addcore:adder|:73
- 2 - C 23 OR2 ! 0 4 0 2 |lpm_add_sub:705|addcore:adder|:63
- 2 - C 20 OR2 ! 0 4 0 2 |lpm_add_sub:705|addcore:adder|:67
- 3 - C 21 OR2 ! 0 4 0 2 |lpm_add_sub:705|addcore:adder|:71
- 2 - C 16 OR2 0 4 0 1 |lpm_add_sub:705|addcore:adder|:83
- 3 - C 20 OR2 0 4 0 1 |lpm_add_sub:705|addcore:adder|:84
- 6 - C 21 OR2 0 4 0 1 |lpm_add_sub:705|addcore:adder|:85
- 1 - C 21 OR2 0 4 0 1 |lpm_add_sub:705|addcore:adder|:86
- 1 - C 14 OR2 s 0 4 0 1 |lpm_add_sub:707|addcore:adder|~86~1
- 7 - C 01 OR2 ! 0 3 0 1 :34
- 6 - C 23 OR2 ! 4 0 0 2 :46
- 6 - C 01 AND2 s 1 3 0 2 ~80~1
- 1 - C 01 AND2 0 3 0 10 :83
- 8 - C 01 OR2 ! 0 3 0 6 :114
- 5 - C 17 OR2 0 4 0 1 :129
- 6 - C 17 DFFE + 0 3 0 2 num_Shift_dividend3 (:154)
- 7 - C 17 DFFE + 0 3 0 2 num_Shift_dividend2 (:155)
- 8 - C 17 DFFE + 0 3 0 2 num_Shift_dividend1 (:156)
- 3 - C 19 DFFE + 0 3 0 3 num_Shift_dividend0 (:157)
- 6 - C 24 DFFE + 0 3 0 2 num_Shift_divisor3 (:181)
- 4 - C 24 DFFE + 0 3 0 3 num_Shift_divisor2 (:182)
- 2 - C 24 DFFE + 0 3 0 4 num_Shift_divisor1 (:183)
- 7 - C 24 DFFE + 0 2 0 5 num_Shift_divisor0 (:184)
- 3 - C 17 OR2 s 0 4 0 1 ~185~1
- 1 - C 17 OR2 0 4 0 5 :185
- 2 - C 17 OR2 ! 0 2 0 1 :186
- 2 - C 01 OR2 ! 0 3 0 6 :200
- 8 - C 14 OR2 ! 0 4 0 11 :215
- 3 - C 14 OR2 ! 0 4 0 7 :250
- 4 - C 13 OR2 0 3 0 1 :271
- 5 - C 20 OR2 0 3 0 1 :272
- 6 - C 16 OR2 0 3 0 1 :273
- 6 - C 13 OR2 0 3 0 1 :289
- 6 - C 20 OR2 0 3 0 1 :290
- 7 - C 16 OR2 0 3 0 1 :291
- 7 - C 20 OR2 0 3 0 1 :318
- 8 - C 16 OR2 0 3 0 1 :319
- 3 - C 13 OR2 s 0 4 0 1 ~325~1
- 4 - C 18 OR2 s ! 0 3 0 1 ~338~1
- 6 - C 18 OR2 s 0 4 0 1 ~338~2
- 7 - C 18 OR2 s 0 4 0 1 ~338~3
- 8 - C 18 OR2 s 0 4 0 1 ~338~4
- 1 - C 18 OR2 s 0 3 0 1 ~339~1
- 8 - C 19 OR2 s 0 3 0 1 ~340~1
- 2 - C 19 OR2 s 0 2 0 13 ~341~1
- 6 - C 19 OR2 s 0 3 0 1 ~341~2
- 1 - C 19 OR2 s 0 2 0 1 ~342~1
- 2 - C 13 DFFE + 0 4 0 4 dividend8 (:343)
- 1 - C 13 DFFE + 0 3 0 10 dividend7 (:344)
- 1 - C 20 DFFE + 1 2 0 9 dividend6 (:345)
- 4 - C 16 DFFE + 1 2 0 11 dividend5 (:346)
- 3 - C 18 DFFE + 1 2 0 10 dividend4 (:347)
- 2 - C 18 DFFE + 1 2 0 2 dividend3 (:348)
- 4 - C 19 DFFE + 1 2 0 2 dividend2 (:349)
- 7 - C 19 DFFE + 1 2 0 2 dividend1 (:350)
- 5 - C 19 DFFE + 1 2 0 1 dividend0 (:351)
- 8 - C 21 OR2 ! 0 4 0 4 :372
- 2 - C 14 OR2 ! 0 4 0 4 :392
- 2 - C 21 OR2 0 4 0 1 :393
- 4 - C 20 OR2 0 4 0 1 :394
- 5 - C 16 OR2 0 4 0 1 :395
- 3 - C 16 AND2 0 3 0 18 :409
- 3 - C 24 OR2 0 3 0 1 :422
- 5 - C 23 OR2 0 3 0 1 :423
- 1 - C 23 OR2 0 3 0 1 :424
- 1 - C 24 DFFE + 1 2 0 13 divisor3 (:434)
- 8 - C 23 DFFE + 1 2 0 8 divisor2 (:435)
- 3 - C 23 DFFE + 1 2 0 7 divisor1 (:436)
- 4 - C 23 DFFE + 1 2 0 9 divisor0 (:437)
- 2 - C 15 OR2 0 2 0 1 :476
- 1 - C 02 WIRE ! 0 0 0 4 :499
- 3 - C 11 OR2 0 3 0 1 :505
- 6 - C 14 OR2 0 4 0 1 :506
- 5 - C 14 OR2 0 3 0 1 :537
- 7 - C 11 AND2 ! 0 4 0 1 :540
- 6 - C 11 OR2 s 0 4 0 1 ~545~1
- 8 - C 11 OR2 0 4 0 2 :545
- 4 - C 11 OR2 s 0 4 0 1 ~546~1
- 5 - C 11 OR2 0 3 0 2 :546
- 7 - C 14 OR2 s 0 4 0 1 ~547~1
- 4 - C 14 OR2 0 4 0 2 :547
- 1 - C 11 DFFE + 0 1 0 7 state2 (:548)
- 2 - C 11 DFFE + 0 1 0 7 state1 (:549)
- 5 - C 01 DFFE + 0 1 0 7 state0 (:550)
- 2 - C 07 AND2 1 2 0 30 :564
- 8 - C 13 OR2 0 4 0 1 :643
- 4 - C 07 DFFE + 0 3 1 0 :660
- 6 - C 07 DFFE + 0 3 1 1 :661
- 1 - C 07 DFFE + 0 3 1 1 :662
- 3 - C 07 DFFE + 0 3 1 1 :663
- 7 - C 07 DFFE + 0 3 1 1 :664
- 5 - C 07 DFFE + 0 3 1 1 :665
- 7 - C 13 DFFE + 0 3 1 1 :666
- 5 - C 13 DFFE + 0 2 1 2 :667
- 8 - C 22 OR2 0 3 1 0 :668
- 7 - C 22 OR2 0 3 0 1 :673
- 6 - C 22 OR2 0 4 0 1 :678
- 3 - C 01 AND2 1 3 1 0 :691
- 4 - C 01 AND2 0 3 1 0 :693
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\verilog hdl\divider_stg_1\divider_stg_1.rpt
divider_stg_1
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 1/ 48( 2%) 0/ 48( 0%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
C: 23/ 96( 23%) 7/ 48( 14%) 33/ 48( 68%) 2/16( 12%) 7/16( 43%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
02: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\verilog hdl\divider_stg_1\divider_stg_1.rpt
divider_stg_1
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 32 clock
Device-Specific Information: d:\verilog hdl\divider_stg_1\divider_stg_1.rpt
divider_stg_1
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 33 reset
Device-Specific Information: d:\verilog hdl\divider_stg_1\divider_stg_1.rpt
divider_stg_1
** EQUATIONS **
clock : INPUT;
reset : INPUT;
start : INPUT;
word10 : INPUT;
word11 : INPUT;
word12 : INPUT;
word13 : INPUT;
word14 : INPUT;
word15 : INPUT;
word16 : INPUT;
word17 : INPUT;
word20 : INPUT;
word21 : INPUT;
word22 : INPUT;
word23 : INPUT;
-- Node name is ':351' = 'dividend0'
-- Equation name is 'dividend0', location is LC5_C19, type is buried.
dividend0 = DFFE( _EQ001, GLOBAL( clock), GLOBAL(!reset), VCC, VCC);
_EQ001 = dividend0 & _LC1_C19 & !_LC2_C7
# _LC2_C7 & word10;
-- Node name is ':350' = 'dividend1'
-- Equation name is 'dividend1', location is LC7_C19, type is buried.
dividend1 = DFFE( _EQ002, GLOBAL( clock), GLOBAL(!reset), VCC, VCC);
_EQ002 = !_LC2_C7 & _LC6_C19
# _LC2_C7 & word11;
-- Node name is ':349' = 'dividend2'
-- Equation name is 'dividend2', location is LC4_C19, type is buried.
dividend2 = DFFE( _EQ003, GLOBAL( clock), GLOBAL(!reset), VCC, VCC);
_EQ003 = !_LC2_C7 & _LC8_C19
# _LC2_C7 & word12;
-- Node name is ':348' = 'dividend3'
-- Equation name is 'dividend3', location is LC2_C18, type is buried.
dividend3 = DFFE( _EQ004, GLOBAL( clock), GLOBAL(!reset), VCC, VCC);
_EQ004 = _LC1_C18 & !_LC2_C7
# _LC2_C7 & word13;
-- Node name is ':347' = 'dividend4'
-- Equation name is 'dividend4', location is LC3_C18, type is buried.
dividend4 = DFFE( _EQ005, GLOBAL( clock), GLOBAL(!reset), VCC, VCC);
_EQ005 = !_LC2_C7 & _LC8_C18
# _LC2_C7 & word14;
-- Node name is ':346' = 'dividend5'
-- Equation name is 'dividend5', location is LC4_C16, type is buried.
dividend5 = DFFE( _EQ006, GLOBAL( clock), GLOBAL(!reset), VCC, VCC);
_EQ006 = !_LC2_C7 & _LC8_C16
# _LC2_C7 & word15;
-- Node name is ':345' = 'dividend6'
-- Equation name is 'dividend6', location is LC1_C20, type is buried.
dividend6 = DFFE( _EQ007, GLOBAL( clock), GLOBAL(!reset), VCC, VCC);
_EQ007 = !_LC2_C7 & _LC7_C20
# _LC2_C7 & word16;
-- Node name is ':344' = 'dividend7'
-- Equation name is 'dividend7', location is LC1_C13, type is buried.
dividend7 = DFFE( _EQ008, GLOBAL( clock), GLOBAL(!reset), VCC, VCC);
_EQ008 = !_LC3_C16 & _LC6_C13
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -