taxi.tan.summary

在Quatus下用VerilogHDL语言编写

--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 12.900 ns
From           : reset
To             : cha0[0]~reg0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 21.600 ns
From           : lpm_counter:min1_rtl_2|alt_counter_f10ke:wysi_counter|q[2]
To             : min1[2]

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 2.300 ns
From           : drive
To             : flagmin[0]~reg0

Type           : Worst-case minimum tco
Slack          : N/A
Required Time  : None
Actual Time    : 14.800 ns
From           : lpm_counter:min1_rtl_2|alt_counter_f10ke:wysi_counter|q[0]
To             : min1[0]

Type           : Clock Setup: 'f64'
Slack          : N/A
Required Time  : None
Actual Time    : 41.32 MHz ( period = 24.200 ns )
From           : minout
To             : cha1[2]~reg0

--------------------------------------------------------------------------------------