taxi.map.summary

来自「在Quatus下用VerilogHDL语言编写」· SUMMARY 代码 · 共 9 行

Analysis & Synthesis Status : Successful - Fri Jul 06 14:03:33 2007
Quartus II Version : 7.1 Build 156 04/30/2007 SJ Web Edition
Revision Name : taxi
Top-level Entity Name : taxi
Family : FLEX10K
Total logic elements : 140
Total pins : 38
Total memory bits : 0