pwm.v

PWM的Verilog HDL代码用于FPGA

// PWM.v
//PWM模块
module PWM(wb_clk_i, wb_rst_i,wb_adr_i, wb_dat_i, wb_dat_o,wb_we_i, wb_cs_i,pwm_out);
parameter clock_divide_reg_init = 32'h0000_0000;
parameter duty_cycle_reg_init   = 32'h0000_0000;	

input        wb_clk_i;     // 主机时钟
input        wb_rst_i;     // 同步复位，高有效
input  [2:0] wb_adr_i;     // 地址输入
input  [7:0] wb_dat_i;     // 数据输入
output [7:0] wb_dat_o;     // 数据输出
input        wb_we_i;      // 写使能
input        wb_cs_i;      // 选择信号
output pwm_out;
reg [31:0] clock_divide_r,duty_cycle_r;
reg [31:0] counter;	
reg [7:0] wb_dat_o;        // 数据总线输出
reg pwm_out;

//计数器进程
always @(posedge wb_clk_i or posedge wb_rst_i)         
begin
	if (wb_rst_i )begin
		          counter <= 0;
	              end
	else
	begin
		if (counter >= clock_divide_r)
			counter <= 0;
		else 
			counter <= counter + 1;
	end
end
//PWM的控制输出进程
always @(posedge wb_clk_i or posedge wb_rst_i)      
begin
	if (wb_rst_i)begin
		pwm_out <= 0;
	end
	else 
	begin
		if (counter <= duty_cycle_r)
			pwm_out <= 1'b1;
		else
			pwm_out <= 1'b0;
	end
end
	
//寄存器的配置状态机
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
	if (wb_rst_i)
	begin
		//initializtion
		clock_divide_r <=clock_divide_reg_init;
		duty_cycle_r <= duty_cycle_reg_init;
	end
	else if ((wb_cs_i&wb_we_i))
	begin
		case (wb_adr_i)
			3'b000:
			begin
				clock_divide_r[7:0] <= wb_dat_i;
			end
			3'b001:
			begin
				clock_divide_r[15:8] <= wb_dat_i;
			end			
			3'b010:
			begin
				clock_divide_r[23:16] <= wb_dat_i;
			end
			3'b011:
			begin
				clock_divide_r[31:24] <= wb_dat_i;
			end			
			3'b100:
			begin
				duty_cycle_r[7:0] <= wb_dat_i;
			end
			3'b101:
			begin
				duty_cycle_r[15:8] <= wb_dat_i;
			end
			3'b110:
			begin
				duty_cycle_r[23:16] <= wb_dat_i;
			end
			3'b111:
			begin
				duty_cycle_r[31:24] <= wb_dat_i;
			end
            default:duty_cycle_r[31:24] <= wb_dat_i;
		endcase
	end
end

//读寄存器进程，仅用来测试用
always @(posedge wb_clk_i)
begin
		case (wb_adr_i)
			3'b000:
			begin
				 wb_dat_o<= clock_divide_r[7:0];
			end
			3'b001:
			begin
				wb_dat_o <= clock_divide_r[15:8];
			end			
			3'b010:
			begin
				wb_dat_o <= clock_divide_r[23:16];
			end
			3'b011:
			begin
				wb_dat_o <= clock_divide_r[31:24];
			end			
			3'b100:
			begin
				wb_dat_o <= duty_cycle_r[7:0];
			end
			3'b101:
			begin
				wb_dat_o <= duty_cycle_r[15:8];
			end
			3'b110:
			begin
				wb_dat_o <= duty_cycle_r[23:16];
			end
			3'b111:
			begin
				wb_dat_o <= duty_cycle_r[31:24];
			end
            default:wb_dat_o <= duty_cycle_r[31:24];
		endcase
end

endmodule