pwm_contr.v

PWM的Verilog HDL代码用于FPGA

// PWM_contr.v

module control(CLK48M,rst,addr,data,CS,WE);

input   CLK48M;
input   rst;

output  CS;                            //片选信号
output  WE;                            //写信号
output  [7:0]   data;                  //数据线
output  [2:0]   addr;                  //地址线  


reg [4:0]  count;                       //分频计数器
reg [4:0]   cou;             
reg [2:0]   bit0,bit1,bit2;             //缓存键值
reg [2:0]   addr;
reg [31:0]  data0,data1;
reg [7:0]   data;
reg     clk1m;
reg     CS;
reg     WE;
reg [4:0]   status;

wire    [2:0]   key_buf;


parameter   div_r = 32'd999;            //分频寄存器
parameter   cyc_r = 32'd249;            //占空比寄存器

parameter  init_pwm = 5'b00001;
parameter  w_div    = 5'b00010;
parameter  w_cyc    = 5'b00100;
parameter  idle     = 5'b01000;

always @(posedge CLK48M or posedge rst)
begin
    if(rst)
        begin
            count <= 5'd0;
            clk1m <= 1'b0;
        end
    else if(count == 5'd24)
        begin
            count <= 5'd0;
            clk1m <= ~clk1m;
        end
      else
        count <= count + 1;
end


always @(posedge clk1m or posedge rst)
begin
    if(rst)
        begin
            CS <= 1'b0;
            WE <= 1'b0;
            addr <= 3'd0;
            data <= 8'd0;
            status <= init_pwm;
            cou <= 5'd0;
        end
    else

        case (status)

    init_pwm :                          //初始化状态
        begin
            WE <= 1'b1;
            CS <= 1'b1;
            cou <= cou + 1;
            if(cou > 5'd10 )
                begin
                    status <= init_pwm;
                    WE <= 1'b0;
                if(cou == 5'd20)
                    begin
                        status <= w_div;
                        cou <= 5'd0;
                    end
                end
            else
                status <= init_pwm;
        end
                                 
    w_div :                             //写分频器寄存器
        begin
            cou <= cou + 1;
            data <= div_r >> (8*addr);
            if(addr == 3'd3)
                begin
                    status <= w_cyc;
                    cou <= 5'd0;
                end
            else
                begin
                    status <= w_div;
                    WE <= 1'b1;
                    if(cou == 5'd3)
                        begin
                            WE <= 1'b0;
                            cou <= 5'd0;
                            addr <= addr + 1; 
                        end
                end
        end
                   

    w_cyc :                             //写占空比寄存器
        begin
            cou <= cou + 1;
            data <= cyc_r >> (addr-4)*8;
            if(addr == 3'd7)
                begin
                    status <= idle;
                    cou <= 5'd0;
                end
            else
                begin
                    status <= w_cyc;
                    WE <= 1'b1;
                    if(cou == 5'd3)
                        begin
                            WE <= 1'b0;
                            cou <= 5'd0;
                            addr <= addr + 1; 
                        end
                end
        end

    idle:
        status <= idle;

        endcase
end


endmodule