top.v

PS2鼠标实验Verilog HDL代码

/****************************************Copyright (c)**************************************************
**                               Guangzhou ZHIYUAN ELECTRONIC CO.,LTD.
**                                      Research centre
**                         http://www.zyinside.com, http://www.zlgmcu.com
**
**---------------------------------------File Info-----------------------------------------------------
** File name:			ps2mouse.v
** Last modified Date:	        2007-7-31
** Last Version:		1.0
** Descriptions:		ps2mouse&UART
**------------------------------------------------------------------------------------------------------
** Created by:	    	 LI WEI
** Created date:		2007-7-31
** Version:			      	1.0
** Descriptions:		The original version
**
**------------------------------------------------------------------------------------------------------
** Modified by:			2007-08-06
** Modified date:		
** Version:				
** Descriptions:		
**
**------------------------------------------------------------------------------------------------------
********************************************************************************************************/
//上电后，按下复位键K2，串口助手BPS设为19200，复位成功后，鼠标应答FAH,否则继续复位。
//成功后，鼠标一有动作就会发送数据，然后串口显示。
/********************************************************************************************************/
module top(clk,reset,ps2mouse_clk,ps2mouse_data,TXD);
 input clk,reset;
 inout ps2mouse_data;
 inout ps2mouse_clk;
 output TXD;
 wire TXD;
 wire  wr_wire;
 wire [7:0]  ps2datawire;
 wire TI;
 wire resetwire;
 ps2mouse   ps2mouse1(
                     .clk(clk),
                     .reset(resetwire),
                     .ps2mouse_clk(ps2mouse_clk),
                     .ps2mouse_data(ps2mouse_data),
                     .data_uart(ps2datawire),
                     .wr_uart(wr_wire)
                     );
 
send      send1     (
			        .clk(clk),								
	        	    .WR(wr_wire),									 
		   	        .Datain(ps2datawire),								
			        .TXD(TXD),									 	
		    	    .TI(TI),
                    .reset(resetwire)									
		   	         );

filter_20ms filter_20ms1(
                         .clk(clk),
                         .in(reset),
                         .out(resetwire)
                         );


endmodule