ddfs.rpt

一个直接数字频率合成的查表程序,VHDL语言,使用7128调试通过

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'F':

                                         Logic cells placed in LAB 'F'
        +------------------------------- LC91 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder1|cout_node
        | +----------------------------- LC96 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder1|g2cp2
        | | +--------------------------- LC93 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder1|g4
        | | | +------------------------- LC87 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder1|result_node0
        | | | | +----------------------- LC95 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder1|result_node2
        | | | | | +--------------------- LC83 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder1|result_node3
        | | | | | | +------------------- LC85 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder1|result_node4
        | | | | | | | +----------------- LC86 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder1|result_node5
        | | | | | | | | +--------------- LC88 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder1|result_node6
        | | | | | | | | | +------------- LC94 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder1|result_node7
        | | | | | | | | | | +----------- LC81 rule15
        | | | | | | | | | | | +--------- LC82 rule14
        | | | | | | | | | | | | +------- LC84 rule13
        | | | | | | | | | | | | | +----- LC90 rule11
        | | | | | | | | | | | | | | +--- LC89 rule9
        | | | | | | | | | | | | | | | +- LC92 rule8
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'F'
LC      | | | | | | | | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'F':
LC96 -> * - - - - - - - - * - - - - - - | - - - - - * - - | <-- |LPM_ADD_SUB:2672|addcore:adder|addcore:adder1|g2cp2
LC93 -> * - - - - - * * * * - - - - - - | - - - - - * - - | <-- |LPM_ADD_SUB:2672|addcore:adder|addcore:adder1|g4
LC81 -> * - - - - - - - - * * - - - - - | - - - - - * - - | <-- rule15
LC82 -> * * - - - - - - * * - * - - - - | - - - - - * - - | <-- rule14
LC84 -> * * - - - - - * * * - - * - - - | - - - - - * - - | <-- rule13
LC90 -> * - * - - * * * * * - - - * - - | - - - - - * - - | <-- rule11
LC89 -> * - * - * * * * * * - - - - * - | - * - - - * - - | <-- rule9
LC92 -> * - * * * * * * * * - - - - - * | - * - - - * - - | <-- rule8

Pin
83   -> - - - - - - - - - - - - - - - - | - - - - - - - - | <-- clk
5    -> - - - - - - - - - - - - * - - - | - - - * - * - - | <-- datin1
6    -> - - - - - - - - - - - * - - - * | - - * - - * - - | <-- datin2
8    -> - - - - - - - - - - * - - - * - | - - * - - * - - | <-- datin3
10   -> - - - - - - - - - - - - - * - - | - - - * - * - - | <-- datin5
11   -> - - - - - - - - - - * * * * * * | - - * * - * - - | <-- datin6
12   -> - - - - - - - - - - * * * * * * | - - * * - * - - | <-- datin7
1    -> - - - - - - - - - - * * * * * * | * * * * * * * * | <-- P12
LC50 -> * - - * * * * * * * - - - - - - | - * - - - * - - | <-- |LPM_ADD_SUB:2672|addcore:adder|addcore:adder0|cout_node
LC56 -> - - - - - - - - - - * * * * * * | - - * * - * * * | <-- state~1
LC55 -> - - - - - - - - - - * * * * * * | - - * * - * * * | <-- state~2
LC54 -> - - - - - - - - - - * * * * * * | - - * * - * * * | <-- state~3
LC19 -> * - - - - - - - - * - - - - - - | - - - - - * - - | <-- count15
LC30 -> * * - - - - - - * * - - - - - - | - - - - - * - - | <-- count14
LC31 -> * * - - - - - * * * - - - - - - | - - - - - * - - | <-- count13
LC32 -> * * - - - - * * * * - - - - - - | - - - - - * - - | <-- count12
LC2  -> * - * - - * * * * * - - - - - - | - - - - - * - - | <-- count11
LC8  -> * - * - * * * * * * - - - - - - | - - - - - * - - | <-- count10
LC79 -> * - * - * * * * * * - - - - - - | - * - - - * - - | <-- count9
LC4  -> * - * * * * * * * * - - - - - - | - * - - - * - - | <-- count8
LC47 -> * * - - - - * * * * - - - - - - | - - * - - * - - | <-- rule12
LC45 -> * - * - * * * * * * - - - - - - | - - * - - * - - | <-- rule10


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                  e:\work\ddfs.rpt
ddfs

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'G':

                   Logic cells placed in LAB 'G'
        +--------- LC109 addr8
        | +------- LC107 addr9
        | | +----- LC105 addr10
        | | | +--- LC104 P13
        | | | | +- LC101 wr
        | | | | | 
        | | | | |   Other LABs fed by signals
        | | | | |   that feed LAB 'G'
LC      | | | | | | A B C D E F G H |     Logic cells that feed LAB 'G':
LC109-> * - - - - | - - - - - - * - | <-- addr8
LC107-> - * - - - | - - - - - - * - | <-- addr9
LC105-> - - * - - | - - - - - - * - | <-- addr10

Pin
83   -> - - - - - | - - - - - - - - | <-- clk
1    -> - - - - * | * * * * * * * * | <-- P12
LC67 -> - - - - * | - - - - - - * - | <-- |LPM_ADD_SUB:2672|addcore:adder|addcore:adder2|result_node6
LC56 -> * * * - - | - - * * - * * * | <-- state~1
LC55 -> * * * - - | - - * * - * * * | <-- state~2
LC54 -> * * * - - | - - * * - * * * | <-- state~3


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                  e:\work\ddfs.rpt
ddfs

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'H':

                                         Logic cells placed in LAB 'H'
        +------------------------------- LC128 addr0
        | +----------------------------- LC126 addr1
        | | +--------------------------- LC125 addr2
        | | | +------------------------- LC123 addr3
        | | | | +----------------------- LC120 addr4
        | | | | | +--------------------- LC118 addr5
        | | | | | | +------------------- LC117 addr6
        | | | | | | | +----------------- LC115 addr7
        | | | | | | | | +--------------- LC114 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder3|result_node0
        | | | | | | | | | +------------- LC116 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder3|result_node1
        | | | | | | | | | | +----------- LC122 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder3|result_node2
        | | | | | | | | | | | +--------- LC127 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder3|result_node3
        | | | | | | | | | | | | +------- LC124 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder3|result_node4
        | | | | | | | | | | | | | +----- LC119 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder3|result_node5
        | | | | | | | | | | | | | | +--- LC121 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder3|result_node6
        | | | | | | | | | | | | | | | +- LC113 count29
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'H'
LC      | | | | | | | | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'H':
LC128-> * - - - - - - - - - - - - - - - | - - - - - - - * | <-- addr0
LC126-> - * - - - - - - - - - - - - - - | - - - - - - - * | <-- addr1
LC125-> - - * - - - - - - - - - - - - - | - - - - - - - * | <-- addr2
LC123-> - - - * - - - - - - - - - - - - | - - - - - - - * | <-- addr3
LC120-> - - - - * - - - - - - - - - - - | - - - - - - - * | <-- addr4
LC118-> - - - - - * - - - - - - - - - - | - - - - - - - * | <-- addr5
LC117-> - - - - - - * - - - - - - - - - | - - - - - - - * | <-- addr6
LC115-> - - - - - - - * - - - - - - - - | - - - - - - - * | <-- addr7
LC119-> - - - - - - - - - - - - - - - * | - - - - - - - * | <-- |LPM_ADD_SUB:2672|addcore:adder|addcore:adder3|result_node5
LC113-> - - - - - * - - - - - - - * * - | - - - - - - - * | <-- count29

Pin
83   -> - - - - - - - - - - - - - - - - | - - - - - - - - | <-- clk
1    -> * * * * * * * - - - - - - - - * | * * * * * * * * | <-- P12
LC71 -> - - - - - - - - * * * * * * * - | - - - - - - - * | <-- |LPM_ADD_SUB:2672|addcore:adder|addcore:adder2|cout_node
LC56 -> * * * * * * * * - - - - - - - - | - - * * - * * * | <-- state~1
LC55 -> * * * * * * * * - - - - - - - - | - - * * - * * * | <-- state~2
LC54 -> * * * * * * * * - - - - - - - - | - - * * - * * * | <-- state~3
LC80 -> - - - - - - * - - - - - - - * - | - - - - - - - * | <-- count30
LC23 -> - - - - * - - - - - - - * * * - | - - - - - - - * | <-- count28
LC17 -> - - - * - - - - - - - * * * * - | - - - - - - - * | <-- count27
LC28 -> - - * - - - - - - - * * * * * - | - - - - - - - * | <-- count26
LC27 -> - * - - - - - - - * * * * * * - | - - - - - - - * | <-- count25
LC25 -> * - - - - - - - * * * * * * * - | - - - - - - - * | <-- count24


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                  e:\work\ddfs.rpt
ddfs

** EQUATIONS **

clk      : INPUT;
datin0   : INPUT;
datin1   : INPUT;
datin2   : INPUT;
datin3   : INPUT;
datin4   : INPUT;
datin5   : INPUT;
datin6   : INPUT;
datin7   : INPUT;
P12      : INPUT;

-- Node name is 'addr0' = ':33' 
-- Equation name is 'addr0', type is output 
 addr0   = DFFE( _EQ001 $ !state~3, GLOBAL( clk), !_EQ002, !_EQ003,  VCC);
  _EQ001 = !addr0 & !state~1 & !state~2 & !state~3
         #  state~1 &  state~2 & !state~3;
  _EQ002 = !count24 & !P12;
  _EQ003 =  count24 & !P12;

-- Node name is 'addr1' = ':31' 
-- Equation name is 'addr1', type is output 
 addr1   = DFFE( _EQ004 $  GND, GLOBAL( clk), !_EQ005, !_EQ006,  VCC);
  _EQ004 =  state~1 & !state~2 &  state~3
         #  addr1 & !state~1 & !state~3
         # !state~1 &  state~2 & !state~3;
  _EQ005 = !count25 & !P12;
  _EQ006 =  count25 & !P12;

-- Node name is 'addr2' = ':29' 
-- Equation name is 'addr2', type is output 
 addr2   = DFFE( _EQ007 $  VCC, GLOBAL( clk), !_EQ008, !_EQ009,  VCC);
  _EQ007 = !state~1 &  state~2 & !state~3
         # !addr2 & !state~1 & !state~3
         #  state~1 & !state~2;
  _EQ008 = !count26 & !P12;
  _EQ009 =  count26 & !P12;

-- Node name is 'addr3' = ':27' 
-- Equation name is 'addr3', type is output 
 addr3   = DFFE( _EQ010 $  GND, GLOBAL( clk), !_EQ011, !_EQ012,  VCC);
  _EQ010 =  addr3 & !state~1 & !state~2 & !state~3;
  _EQ011 = !count27 & !P12;
  _EQ012 =  count27 & !P12;

-- Node name is 'addr4' = ':25' 
-- Equation name is 'addr4', type is output 
 addr4   = DFFE( _EQ013 $  VCC, GLOBAL( clk), !_EQ014, !_EQ015,  VCC);
  _EQ013 = !addr4 & !state~1 & !state~2 & !state~3;
  _EQ014 = !count28 & !P12;
  _EQ015 =  count28 & !P12;

-- Node name is 'addr5' = ':23' 
-- Equation name is 'addr5', type is output 
 addr5   = DFFE( _EQ016 $  GND, GLOBAL( clk), !_EQ017, !_EQ018,  VCC);
  _EQ016 =  addr5 & !state~1 & !state~2 & !state~3;
  _EQ017 = !count29 & !P12;
  _EQ018 =  count29 & !P12;

-- Node name is 'addr6' = ':21' 
-- Equation name is 'addr6', type is output 
 addr6   = DFFE( _EQ019 $  VCC, GLOBAL( clk), !_EQ020, !_EQ021,  VCC);
  _EQ019 = !addr6 & !state~1 & !state~2 & !state~3;
  _EQ020 = !count30 & !P12;
  _EQ021 =  count30 & !P12;

-- Node name is 'addr7' = ':19' 
-- Equation name is 'addr7', type is output 
 addr7   = DFFE( _EQ022 $  GND, GLOBAL( clk), GLOBAL( P12),  VCC,  VCC);
  _EQ022 =  addr7 & !state~1 & !state~2 & !state~3;

-- Node name is 'addr8' = ':17' 
-- Equation name is 'addr8', type is output 
 addr8   = DFFE( _EQ023 $  GND, GLOBAL( clk), GLOBAL( P12),  VCC,  VCC);
  _EQ023 =  addr8 & !state~1 & !state~2 & !state~3;

-- Node name is 'addr9' = ':15' 
-- Equation name is 'addr9', type is output 
 addr9   = DFFE( _EQ024 $  GND, GLOBAL( clk), GLOBAL( P12),  VCC,  VCC);
  _EQ024 =  addr9 & !state~1 & !state~2 & !state~3;