📄 ddfs.rpt
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Total flipflops required: 69
Total product terms required: 339
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 44
Synthesized logic cells: 0/ 128 ( 0%)
Device-Specific Information: e:\work\ddfs.rpt
ddfs
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
83 - - INPUT G 0 0 0 0 0 0 0 clk
4 (16) (A) INPUT 0 0 0 0 0 0 4 datin0
5 (14) (A) INPUT 0 0 0 0 0 0 4 datin1
6 (13) (A) INPUT 0 0 0 0 0 0 4 datin2
8 (11) (A) INPUT 0 0 0 0 0 0 4 datin3
9 (8) (A) INPUT 0 0 0 0 0 0 4 datin4
10 (6) (A) INPUT 0 0 0 0 0 0 4 datin5
11 (5) (A) INPUT 0 0 0 0 0 0 27 datin6
12 (3) (A) INPUT 0 0 0 0 0 0 27 datin7
1 - - INPUT G 0 0 0 0 0 8 57 P12
67 104 G BIDIR 0 0 0 0 0 0 0 P13
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\work\ddfs.rpt
ddfs
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
81 128 H FF + t 1 0 1 1 5 1 0 addr0
80 126 H FF + t 1 0 1 1 5 1 0 addr1
79 125 H FF + t 1 0 1 1 5 1 0 addr2
77 123 H FF + t 0 0 0 1 5 1 0 addr3
76 120 H FF + t 0 0 0 1 5 1 0 addr4
75 118 H FF + t 0 0 0 1 5 1 0 addr5
74 117 H FF + t 0 0 0 1 5 1 0 addr6
73 115 H FF + t 0 0 0 0 4 1 0 addr7
70 109 G FF + t 0 0 0 0 4 1 0 addr8
69 107 G FF + t 0 0 0 0 4 1 0 addr9
68 105 G FF + t 0 0 0 0 4 1 0 addr10
67 104 G TRI t 0 0 0 0 0 0 0 P13
65 101 G FF + t ! 0 0 0 1 1 0 4 wr (:45)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\work\ddfs.rpt
ddfs
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 50 D SOFT t 6 5 1 0 9 0 9 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder0|cout_node
- 44 C SOFT t 2 2 0 0 6 0 1 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder0|gcp2
- 39 C SOFT t 4 4 0 0 8 0 5 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder0|g4
(28) 40 C SOFT t 0 0 0 0 2 0 1 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder0|result_node0
(24) 46 C SOFT t 3 2 0 0 6 0 1 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder0|result_node2
(23) 48 C SOFT t 2 2 0 0 3 0 1 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder0|result_node3
(39) 53 D SOFT t 2 1 0 0 3 0 1 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder0|result_node4
- 62 D SOFT t 3 2 0 0 5 0 1 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder0|result_node5
- 63 D SOFT t 4 3 0 0 7 0 1 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder0|result_node6
(33) 64 D SOFT t 6 5 1 0 9 0 1 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder0|result_node7
(58) 91 F SOFT t 9 9 0 0 19 0 9 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder1|cout_node
(62) 96 F SOFT t 2 2 0 0 6 0 2 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder1|g2cp2
(60) 93 F SOFT t 4 4 0 0 8 0 5 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder1|g4
- 87 F SOFT t 0 0 0 0 3 0 1 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder1|result_node0
(15) 29 B SOFT t 3 2 0 0 5 0 1 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder1|result_node1
- 95 F SOFT t 4 3 0 0 7 0 1 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder1|result_node2
(54) 83 F SOFT t 6 5 1 0 9 0 1 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder1|result_node3
(55) 85 F SOFT t 6 5 0 0 12 0 1 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder1|result_node4
(56) 86 F SOFT t 7 6 0 0 14 0 1 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder1|result_node5
(57) 88 F SOFT t 9 7 1 0 16 0 1 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder1|result_node6
(61) 94 F SOFT t 9 9 0 0 19 0 1 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder1|result_node7
- 71 E SOFT t 9 9 0 0 19 0 7 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder2|cout_node
(48) 72 E SOFT t 2 2 0 0 6 0 2 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder2|g2cp2
(49) 73 E SOFT t 4 4 0 0 8 0 5 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder2|g4
- 74 E SOFT t 0 0 0 0 3 0 1 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder2|result_node0
- 9 A SOFT t 3 2 0 0 5 0 1 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder2|result_node1
(51) 77 E SOFT t 4 3 0 0 7 0 1 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder2|result_node2
- 66 E SOFT t 6 5 1 0 9 0 1 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder2|result_node3
- 68 E SOFT t 6 5 0 0 12 0 1 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder2|result_node4
- 78 E SOFT t 7 6 0 0 14 0 1 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder2|result_node5
(45) 67 E SOFT t 9 7 1 0 16 1 0 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder2|result_node6
(46) 69 E SOFT t 9 9 0 0 19 0 1 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder2|result_node7
- 114 H SOFT t 0 0 0 0 2 0 1 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder3|result_node0
- 116 H SOFT t 0 0 0 0 3 0 1 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder3|result_node1
- 122 H SOFT t 0 0 0 0 4 0 1 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder3|result_node2
- 127 H SOFT t 0 0 0 0 5 0 1 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder3|result_node3
- 124 H SOFT t 0 0 0 0 6 0 1 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder3|result_node4
- 119 H SOFT t 0 0 0 0 7 0 1 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder3|result_node5
- 121 H SOFT t 0 0 0 0 8 0 1 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder3|result_node6
(37) 56 D DFFE + t 1 0 1 3 3 11 27 state~1
- 55 D TFFE + t 0 0 0 3 3 11 27 state~2
- 54 D DFFE + t 0 0 0 3 3 11 27 state~3
(52) 80 E DFFE + t 0 0 0 1 1 1 1 count30 (:37)
- 113 H DFFE + t 0 0 0 1 1 1 2 count29 (:38)
- 23 B DFFE + t 0 0 0 1 1 1 3 count28 (:39)
(22) 17 B DFFE + t 0 0 0 1 1 1 4 count27 (:40)
- 28 B DFFE + t 0 0 0 1 1 1 5 count26 (:41)
(16) 27 B DFFE + t 0 0 0 1 1 1 6 count25 (:42)
(17) 25 B DFFE + t 0 0 0 1 1 1 7 count24 (:43)
- 22 B DFFE + t 0 0 0 1 1 0 2 count23 (:44)
(20) 21 B DFFE + t 0 0 0 1 1 0 5 count21 (:46)
- 20 B DFFE + t 0 0 0 1 1 0 6 count20 (:47)
- 26 B DFFE + t 0 0 0 1 1 0 7 count19 (:48)
(18) 24 B DFFE + t 0 0 0 1 1 0 8 count18 (:49)
(44) 65 E DFFE + t 0 0 0 1 1 0 9 count17 (:50)
- 18 B DFFE + t 0 0 0 1 1 0 10 count16 (:51)
(21) 19 B DFFE + t 0 0 0 1 1 0 2 count15 (:52)
- 30 B DFFE + t 0 0 0 1 1 0 4 count14 (:53)
- 31 B DFFE + t 0 0 0 1 1 0 5 count13 (:54)
(14) 32 B DFFE + t 0 0 0 1 1 0 6 count12 (:55)
- 2 A DFFE + t 0 0 0 1 1 0 7 count11 (:56)
(9) 8 A DFFE + t 0 0 0 1 1 0 8 count10 (:57)
- 79 E DFFE + t 0 0 0 1 1 0 9 count9 (:58)
- 4 A DFFE + t 0 0 0 1 1 0 10 count8 (:59)
- 70 E DFFE + t 0 0 0 1 1 0 2 count7 (:60)
- 76 E DFFE + t 0 0 0 1 1 0 3 count6 (:61)
(50) 75 E DFFE + t 0 0 0 1 1 0 4 count5 (:62)
- 12 A DFFE + t 0 0 0 1 1 0 5 count4 (:63)
(8) 11 A DFFE + t 0 0 0 1 1 0 2 count3 (:64)
- 10 A DFFE + t 0 0 0 1 1 0 3 count2 (:65)
(27) 43 C DFFE + t 2 1 0 1 4 0 4 count1 (:66)
- 1 A DFFE + t 0 0 0 1 1 0 5 count0 (:67)
(40) 51 D TFFE + t 1 0 1 4 4 0 3 rule23 (:68)
- 36 C TFFE + t 1 0 1 4 4 0 5 rule22 (:69)
- 34 C TFFE + t 1 0 1 4 4 0 6 rule21 (:70)
- 33 C TFFE + t 1 0 1 4 4 0 7 rule20 (:71)
(41) 49 D TFFE + t 1 0 1 4 4 0 8 rule19 (:72)
- 42 C TFFE + t 1 0 1 4 4 0 9 rule18 (:73)
- 58 D TFFE + t 0 0 0 4 4 0 10 rule17 (:74)
- 41 C TFFE + t 0 0 0 4 4 0 11 rule16 (:75)
- 81 F TFFE + t 0 0 0 4 4 0 3 rule15 (:76)
- 82 F TFFE + t 0 0 0 4 4 0 5 rule14 (:77)
- 84 F TFFE + t 0 0 0 4 4 0 6 rule13 (:78)
- 47 C TFFE + t 0 0 0 4 4 0 7 rule12 (:79)
- 90 F TFFE + t 0 0 0 4 4 0 8 rule11 (:80)
(25) 45 C TFFE + t 0 0 0 4 4 0 9 rule10 (:81)
- 89 F TFFE + t 0 0 0 4 4 0 10 rule9 (:82)
- 92 F TFFE + t 0 0 0 4 4 0 11 rule8 (:83)
(34) 61 D TFFE + t 0 0 0 4 4 0 3 rule7 (:84)
- 60 D TFFE + t 0 0 0 4 4 0 4 rule6 (:85)
(35) 59 D TFFE + t 0 0 0 4 4 0 5 rule5 (:86)
- 52 D TFFE + t 0 0 0 4 4 0 6 rule4 (:87)
(30) 37 C TFFE + t 0 0 0 4 4 0 3 rule3 (:88)
(29) 38 C TFFE + t 0 0 0 4 4 0 4 rule2 (:89)
(36) 57 D TFFE + t 0 0 0 4 4 0 5 rule1 (:90)
(31) 35 C TFFE + t 0 0 0 4 4 0 6 rule0 (:91)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\work\ddfs.rpt
ddfs
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+--------------- LC9 |LPM_ADD_SUB:2672|addcore:adder|addcore:adder2|result_node1
| +------------- LC2 count11
| | +----------- LC8 count10
| | | +--------- LC4 count8
| | | | +------- LC12 count4
| | | | | +----- LC11 count3
| | | | | | +--- LC10 count2
| | | | | | | +- LC1 count0
| | | | | | | |
| | | | | | | | Other LABs fed by signals
| | | | | | | | that feed LAB 'A'
LC | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'A':
Pin
83 -> - - - - - - - - | - - - - - - - - | <-- clk
1 -> - * * * * * * * | * * * * * * * * | <-- P12
LC40 -> - - - - - - - * | * - - - - - - - | <-- |LPM_ADD_SUB:2672|addcore:adder|addcore:adder0|result_node0
LC46 -> - - - - - - * - | * - - - - - - - | <-- |LPM_ADD_SUB:2672|addcore:adder|addcore:adder0|result_node2
LC48 -> - - - - - * - - | * - - - - - - - | <-- |LPM_ADD_SUB:2672|addcore:adder|addcore:adder0|result_node3
LC53 -> - - - - * - - - | * - - - - - - - | <-- |LPM_ADD_SUB:2672|addcore:adder|addcore:adder0|result_node4
LC91 -> * - - - - - - - | * - - - * - - - | <-- |LPM_ADD_SUB:2672|addcore:adder|addcore:adder1|cout_node
LC87 -> - - - * - - - - | * - - - - - - - | <-- |LPM_ADD_SUB:2672|addcore:adder|addcore:adder1|result_node0
LC95 -> - - * - - - - - | * - - - - - - - | <-- |LPM_ADD_SUB:2672|addcore:adder|addcore:adder1|result_node2
LC83 -> - * - - - - - - | * - - - - - - - | <-- |LPM_ADD_SUB:2672|addcore:adder|addcore:adder1|result_node3
LC65 -> * - - - - - - - | * - - - * - - - | <-- count17
LC18 -> * - - - - - - - | * - - - * - - - | <-- count16
LC58 -> * - - - - - - - | * - - * * - - - | <-- rule17
LC41 -> * - - - - - - - | * - * - * - - - | <-- rule16
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\work\ddfs.rpt
ddfs
** LOGIC CELL INTERCONNECTIONS **
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