📄 ddfs.rpt
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Project Information e:\work\ddfs.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 05/12/2005 10:22:56
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
DDFS
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
ddfs EPM7128SLC84-15 10 12 1 109 48 85 %
User Pins: 10 12 1
Project Information e:\work\ddfs.rpt
** PROJECT COMPILATION MESSAGES **
Warning: GLOBAL primitive on node 'P12' feeds logic -- non-global signal usage may result
Project Information e:\work\ddfs.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'clk' chosen for auto global Clock
INFO: Signal 'P12' chosen for auto global Clear
Project Information e:\work\ddfs.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
ddfs@81 addr0
ddfs@80 addr1
ddfs@79 addr2
ddfs@77 addr3
ddfs@76 addr4
ddfs@75 addr5
ddfs@74 addr6
ddfs@73 addr7
ddfs@70 addr8
ddfs@69 addr9
ddfs@68 addr10
ddfs@83 clk
ddfs@4 datin0
ddfs@5 datin1
ddfs@6 datin2
ddfs@8 datin3
ddfs@9 datin4
ddfs@10 datin5
ddfs@11 datin6
ddfs@12 datin7
ddfs@1 P12
ddfs@67 P13
ddfs@65 wr
Project Information e:\work\ddfs.rpt
** STATE MACHINE ASSIGNMENTS **
state: MACHINE
OF BITS (
state~3,
state~2,
state~1
)
WITH STATES (
s0 = B"000",
s1 = B"001",
s2 = B"101",
s3 = B"010",
s4 = B"011"
);
Project Information e:\work\ddfs.rpt
** FILE HIERARCHY **
|lpm_add_sub:2672|
|lpm_add_sub:2672|addcore:adder|
|lpm_add_sub:2672|addcore:adder|addcore:adder3|
|lpm_add_sub:2672|addcore:adder|addcore:adder2|
|lpm_add_sub:2672|addcore:adder|addcore:adder1|
|lpm_add_sub:2672|addcore:adder|addcore:adder0|
|lpm_add_sub:2672|altshift:result_ext_latency_ffs|
|lpm_add_sub:2672|altshift:carry_ext_latency_ffs|
|lpm_add_sub:2672|altshift:oflow_ext_latency_ffs|
Device-Specific Information: e:\work\ddfs.rpt
ddfs
***** Logic for device 'ddfs' compiled without errors.
Device: EPM7128SLC84-15
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffff
MultiVolt I/O = OFF
d d d d d d d V
a a a a a a a C a a a V a a a
t t t t t t t C d d d C d d d
i i i i G i i i I G P G c G d d d C d d d
n n n n N n n n N N 1 N l N r r r I r r r
6 5 4 3 D 2 1 0 T D 2 D k D 0 1 2 O 3 4 5
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
datin7 | 12 74 | addr6
VCCIO | 13 73 | addr7
#TDI | 14 72 | GND
RESERVED | 15 71 | #TDO
RESERVED | 16 70 | addr8
RESERVED | 17 69 | addr9
RESERVED | 18 68 | addr10
GND | 19 67 | P13
RESERVED | 20 66 | VCCIO
RESERVED | 21 65 | wr
RESERVED | 22 EPM7128SLC84-15 64 | RESERVED
#TMS | 23 63 | RESERVED
RESERVED | 24 62 | #TCK
RESERVED | 25 61 | RESERVED
VCCIO | 26 60 | RESERVED
RESERVED | 27 59 | GND
RESERVED | 28 58 | RESERVED
RESERVED | 29 57 | RESERVED
RESERVED | 30 56 | RESERVED
RESERVED | 31 55 | RESERVED
GND | 32 54 | RESERVED
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
R R R R R V R R R G V R R R G R R R R R V
E E E E E C E E E N C E E E N E E E E E C
S S S S S C S S S D C S S S D S S S S S C
E E E E E I E E E I E E E E E E E E I
R R R R R O R R R N R R R R R R R R O
V V V V V V V V T V V V V V V V V
E E E E E E E E E E E E E E E E
D D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: e:\work\ddfs.rpt
ddfs
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 8/16( 50%) 8/ 8(100%) 3/16( 18%) 13/36( 36%)
B: LC17 - LC32 16/16(100%) 1/ 8( 12%) 3/16( 18%) 21/36( 58%)
C: LC33 - LC48 16/16(100%) 1/ 8( 12%) 10/16( 62%) 26/36( 72%)
D: LC49 - LC64 16/16(100%) 0/ 8( 0%) 13/16( 81%) 23/36( 63%)
E: LC65 - LC80 16/16(100%) 0/ 8( 0%) 16/16(100%) 26/36( 72%)
F: LC81 - LC96 16/16(100%) 1/ 8( 12%) 16/16(100%) 29/36( 80%)
G: LC97 - LC112 5/16( 31%) 6/ 8( 75%) 0/16( 0%) 8/36( 22%)
H: LC113 - LC128 16/16(100%) 8/ 8(100%) 3/16( 18%) 21/36( 58%)
Total dedicated input pins used: 2/4 ( 50%)
Total I/O pins used: 25/64 ( 39%)
Total logic cells used: 109/128 ( 85%)
Total shareable expanders used: 48/128 ( 37%)
Total Turbo logic cells used: 109/128 ( 85%)
Total shareable expanders not available (n/a): 16/128 ( 12%)
Average fan-in: 6.74
Total fan-in: 735
Total input pins required: 10
Total fast input logic cells required: 0
Total output pins required: 12
Total bidirectional pins required: 1
Total reserved pins required 4
Total logic cells required: 109
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