ddfs.tdf

一个直接数字频率合成的查表程序,VHDL语言,使用7128调试通过

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
 
ENTITY ddfs IS 
   PORT (clk,P25 : IN Std_logic; 
         datin : IN Std_logic_vector(7 DOWNTO 0);
         addr: OUT Std_logic_vector(7 DOWNTO 0);
         tc,P24: OUT Std_logic);
END ddfs;

ARCHITECTURE using_std_logic OF ddfs IS
 
   SIGNAL count : Std_logic_vector(30 DOWNTO 0);
   SIGNAL count1 : Std_logic_vector(23 DOWNTO 0);
   SIGNAL rule : Std_logic_vector(30 DOWNTO 0);
   SIGNAL a,b,c:Std_logic_vector(7 DOWNTO 0);
   TYPE STATE_TYPE IS (s0, s1,s2,S3);
   SIGNAL state	: STATE_TYPE;
BEGIN

   PROCESS(clk)
   BEGIN
    IF P25='0' THEN
                    addr<= count(30 DOWNTO 23);
                    state <= s0;
	ELSIF (clk'EVENT AND clk = '1') THEN
      CASE state IS
                WHEN s0=>
                    state<=s1;
				WHEN s1=>
                    addr<="01010001";
                    a<=datin;
					state <= s2;
				WHEN s2=>
                    addr<="01010010";
                    b<=datin;
                    state <= s3;
                WHEN S3=>
                    addr<="01010011";
                    c<=datin;
                    rule<="0000000"&c&b&a;
                    state<=s1;
        END CASE;
      END IF;  
    END PROCESS;
  
   PROCESS(clk)
   BEGIN
      IF (clk'EVENT AND clk = '1') THEN
         IF P25='1' THEN
           count<="0000000000000000000000000000000";
         else
           count <= count + rule;
         END IF;
      END IF; 
   END PROCESS;
   p24<='1' when count="111111111111111111111111";
   tc <= '1' WHEN count = "0000000000000000000000000000000" ELSE '0';
END using_std_logic;