fr.txt

基于FPGA的数字频率计的设计

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity multi is
       port(f1khz,q_over	:	in	std_logic;
	  	  dp1,dp2	:	in	std_logic;	
	      freq_value0,freq_value1	:	in	std_logic_vector(3 downto 0);
		 freq_value2,freq_value3	:	in	std_logic_vector(3 downto 0);
		 freq_value4,freq_value5	:	in	std_logic_vector(3 downto 0);
		 out0,out1,out2,out3,out4,out5:	out 	std_logic_vector(6 downto 0));
end multi;
architecture Behavioral of multi is
	signal 	sel		:	std_logic_vector(2 downto 0):="000";
	signal 	hide		:	std_logic; 
	signal 	data		:	std_logic_vector(3 downto 0);
	signal	led		:	std_logic_vector(6 downto 0);	
begin
	scan : process (f1khz)
   		begin
      		if rising_edge(f1khz) then
	 			if sel  = "101" then
	    			sel <= "000";
	 			else
	    			sel <= sel + 1;
	 			end if;
      		end if;
   		end process;
	mux:process(sel,freq_value0,freq_value1,freq_value2,freq_value3,freq_value4,freq_value5)
   		begin
      	case sel is
	 		when "000" =>	data <= freq_value0;
	 		when "001" =>	data <= freq_value1;
	 		when "010" =>	data <= freq_value2;
	 		when "011" =>	data <= freq_value3;
	 		when "100" =>	data <= freq_value4;
	 		when others =>	data <= freq_value5;
      	end case;
   		end process;
	bcd2led : process (hide,data)
   		begin
      	led <= "1111111";
      	if hide /= '1' then
	 		case data is
	    		when "0000" =>  led <= "0000001";	
	    		when "0001" =>  led <= "1001111";	
	    		when "0010" =>  led <= "0010010";	
	    		when "0011" =>  led <= "0000110";	
	    		when "0100" =>  led <= "1001100";	
	    		when "0101" =>  led <= "0100100";	
	    		when "0110" =>  led <= "0100000";	
	    		when "0111" =>  led <= "0001111";	
	    		when "1000" =>  led <= "0000000";
	    		when "1001" =>  led <= "0000100";
	    		when others =>  null;
	 		end case;
      	end if;
   		end process;
	fenpei:process(sel,led)
			begin
			out0<="1111111";
		     out1<="1111111";
		     out2<="1111111";
		     out3<="1111111";
		     out4<="1111111";
		     out5<="1111111";	
				case sel is
					when "000" => out0 <= led;
					when "001" => out1 <= led;
					when "010" => out2 <= led;
					when "011" => out3 <= led;
					when "100" => out4 <= led;
					when "101" => out5 <= led;
					when others => null;
				end case;
		end process;	
   	hide_zero:process (sel,q_over,dp1,dp2,freq_value5,freq_value4,freq_value3,freq_value2)
   		begin
      	hide <= '0';
      	case sel is
	 	when "101" =>
	    		if q_over = '0' and freq_value5 = "0000"
	       		then hide <= '1';
	    		end if;
	 	when "100" =>
	    		if q_over = '0' and freq_value5 = "0000"
				and freq_value4 = "0000"
	       		then hide <= '1';
	    		end if;
	 	when "011" =>
	    		if q_over = '0' and freq_value5 = "0000"
			    	and freq_value4 = "0000"
			    	and freq_value3 = "0000"
			    	and dp1 /= '1'
	       	then hide <= '1';
	    		end if;
	 	when "010" =>
	    		if q_over = '0' and freq_value5 = "0000"
			    	and freq_value4 = "0000"
			    	and freq_value3 = "0000"
			    	and freq_value2 = "0000"
			    	and dp1 /= '1'
			    	and dp2 /= '1'
	       	then hide <= '1';
	    		end if;
	 	when others =>
	    		null;
      	end case;
   		end process;
end Behavioral;