content.edn

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EDN
1,950 行
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(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0))
(status (written (timeStamp 2007 7 15 17 55 50)
   (author "Xilinx, Inc.")
   (program "Xilinx CORE Generator" (version "Xilinx CORE Generator 6.3i"))))
   (comment "                                                                                
      This file is owned and controlled by Xilinx and must be used              
      solely for design, simulation, implementation and creation of             
      design files limited to Xilinx devices or technologies. Use               
      with non-Xilinx devices or technologies is expressly prohibited           
      and immediately terminates your license.                                  
                                                                                
      XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 'AS IS'             
      SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                   
      XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION           
      AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION               
      OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                 
      IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                   
      AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE          
      FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                  
      WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                   
      IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR            
      REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF           
      INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS           
      FOR A PARTICULAR PURPOSE.                                                 
                                                                                
      Xilinx products are not intended for use in life support                  
      appliances, devices, or systems. Use in such applications are             
      expressly prohibited.                                                     
                                                                                
      (c) Copyright 1995-2004 Xilinx, Inc.                                      
      All rights reserved.                                                      
                                                                                
   ")
   (comment "Core parameters: ")
       (comment "c_use_blockmem = 0 ")
       (comment "c_rd_count_width = 2 ")
       (comment "c_has_wr_ack = 0 ")
       (comment "c_has_almost_full = 0 ")
       (comment "c_has_wr_err = 0 ")
       (comment "c_wr_err_low = 0 ")
       (comment "c_wr_ack_low = 0 ")
       (comment "c_data_width = 16 ")
       (comment "c_enable_rlocs = 0 ")
       (comment "c_rd_err_low = 0 ")
       (comment "c_rd_ack_low = 0 ")
       (comment "c_wr_count_width = 2 ")
       (comment "InstanceName = content ")
       (comment "c_has_rd_count = 0 ")
       (comment "c_has_almost_empty = 0 ")
       (comment "c_has_rd_ack = 0 ")
       (comment "c_has_wr_count = 0 ")
       (comment "c_fifo_depth = 31 ")
       (comment "c_has_rd_err = 0 ")
   (external xilinxun (edifLevel 0)
      (technology (numberDefinition))
       (cell VCC (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port P (direction OUTPUT))
               )
           )
       )
       (cell GND (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port G (direction OUTPUT))
               )
           )
       )
       (cell FDCE (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port D (direction INPUT))
                   (port C (direction INPUT))
                   (port CE (direction INPUT))
                   (port CLR (direction INPUT))
                   (port Q (direction OUTPUT))
               )
           )
       )
       (cell FDE (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port D (direction INPUT))
                   (port C (direction INPUT))
                   (port CE (direction INPUT))
                   (port Q (direction OUTPUT))
               )
           )
       )
       (cell FDPE (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port D (direction INPUT))
                   (port C (direction INPUT))
                   (port CE (direction INPUT))
                   (port PRE (direction INPUT))
                   (port Q (direction OUTPUT))
               )
           )
       )
       (cell LUT4 (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port I0 (direction INPUT))
                   (port I1 (direction INPUT))
                   (port I2 (direction INPUT))
                   (port I3 (direction INPUT))
                   (port O (direction OUTPUT))
               )
           )
       )
       (cell MUXCY (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port DI (direction INPUT))
                   (port CI (direction INPUT))
                   (port S (direction INPUT))
                   (port O (direction OUTPUT))
               )
           )
       )
       (cell MUXCY_D (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port DI (direction INPUT))
                   (port CI (direction INPUT))
                   (port S (direction INPUT))
                   (port O (direction OUTPUT))
                   (port LO (direction OUTPUT))
               )
           )
       )
       (cell MUXCY_L (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port DI (direction INPUT))
                   (port CI (direction INPUT))
                   (port S (direction INPUT))
                   (port LO (direction OUTPUT))
               )
           )
       )
       (cell RAM16X1D (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port D (direction INPUT))
                   (port WE (direction INPUT))
                   (port WCLK (direction INPUT))
                   (port A0 (direction INPUT))
                   (port A1 (direction INPUT))
                   (port A2 (direction INPUT))
                   (port A3 (direction INPUT))
                   (port DPRA0 (direction INPUT))
                   (port DPRA1 (direction INPUT))
                   (port DPRA2 (direction INPUT))
                   (port DPRA3 (direction INPUT))
                   (port SPO (direction OUTPUT))
                   (port DPO (direction OUTPUT))
               )
           )
       )
       (cell XORCY (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port LI (direction INPUT))
                   (port CI (direction INPUT))
                   (port O (direction OUTPUT))
               )
           )
       )
   )
(library test_lib (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit Time))))
(cell content
 (cellType GENERIC) (view view_1 (viewType NETLIST)
  (interface
   (port ( array ( rename din "din<15:0>") 16 ) (direction INPUT))
   (port ( rename wr_en "wr_en") (direction INPUT))
   (port ( rename wr_clk "wr_clk") (direction INPUT))
   (port ( rename rd_en "rd_en") (direction INPUT))
   (port ( rename rd_clk "rd_clk") (direction INPUT))
   (port ( rename ainit "ainit") (direction INPUT))
   (port ( array ( rename dout "dout<15:0>") 16 ) (direction OUTPUT))
   (port ( rename full "full") (direction OUTPUT))
   (port ( rename empty "empty") (direction OUTPUT))
   )
  (contents
   (instance VCC (viewRef view_1 (cellRef VCC  (libraryRef xilinxun))))
   (instance GND (viewRef view_1 (cellRef GND  (libraryRef xilinxun))))
   (instance BU15
      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
      (property INIT (string "4444"))
   )
   (instance BU20
      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
      (property INIT (string "8888"))
   )
   (instance BU22
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU23
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU24
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU25
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU26
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU27
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU28
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU29
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU30
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU31
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU32
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU33
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU34
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU35
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU36
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU37
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU39
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU40
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU41
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU42
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU43
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU44
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU45
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU46
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU47
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU48
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU49
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU50
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU51
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU52
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU53
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU54
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance BU63
      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
      (property INIT (string "caca"))
   )
   (instance BU64
      (viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
   )
   (instance BU69
      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
      (property INIT (string "caca"))
   )
   (instance BU70
      (viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
   )
   (instance BU75
      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
      (property INIT (string "caca"))
   )
   (instance BU76
      (viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
   )
   (instance BU81
      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
      (property INIT (string "caca"))
   )
   (instance BU82
      (viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
   )
   (instance BU87
      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
      (property INIT (string "caca"))
   )
   (instance BU88
      (viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
   )
   (instance BU93
      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
      (property INIT (string "caca"))
   )
   (instance BU94
      (viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
   )
   (instance BU99
      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
      (property INIT (string "caca"))
   )
   (instance BU100
      (viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
   )
   (instance BU105
      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
      (property INIT (string "caca"))
   )
   (instance BU106
      (viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
   )
   (instance BU111
      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
      (property INIT (string "caca"))
   )
   (instance BU112
      (viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
   )
   (instance BU117
      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
12345

content.edn - 源码说明

本页面展示了「具备GMII接口和ARP协议功能的千兆以太网控制器。经过Xilinx SPATAN-III FPGA验证, Verilog描述」中的 content.edn 源码文件，采用 EDN 编程语言编写，共 1,950 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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