r_arp.v

来自「具备GMII接口和ARP协议功能的千兆以太网控制器。经过Xilinx SPATA」· Verilog 代码 · 共 151 行

module r_arp(
             clk,
             rst,
             arp_en,
             arp_data,
             a_des_add,
             a_des_ip,
             r_des_add,
             r_des_ip,
             r_empty,
             r_rd
             );
    input clk;
    input rst;
    input arp_en;
    input [7:0] arp_data;
    output [47:0] a_des_add;
    reg[47:0] a_des_add;
    output [31:0] a_des_ip;
    reg[31:0] a_des_ip;
    output [47:0] r_des_add;
    reg[47:0] r_des_add;
    output [31:0] r_des_ip;
    reg[31:0] r_des_ip;
    output r_empty;
    reg r_empty;
    input r_rd;
    
    reg[5:0] current;
    reg[5:0] next;
 
    reg[5:0] counter;	    //modified rignal reg[3:0] counter;
    //reg[7:0] operator;
    
    parameter IDLE=6'h01, OP=6'h02, ARP=6'h04, R_ARP=6'h08,LATCH=6'h10,UNK=6'h20;
    
always@(current or arp_en or counter or arp_data)
begin
	next=6'bxxxx_xx;
	case(current)
	IDLE: begin
		if(arp_en)
		next=OP;
		else
		next=IDLE;
	end
	OP:begin
		if(counter==7) begin
			if(arp_data==1)
			next=R_ARP;
			else if(arp_data==2)
			next=ARP;
			else
			next=UNK;
		end
		else
		next=OP;
	end
	ARP:begin
		if(!arp_en)
		next=IDLE;
		else
		next=ARP;
	end
	R_ARP:begin
		if(!arp_en)
		next=LATCH;
		else
		next=R_ARP;
	end
	LATCH: next=IDLE;
	UNK: begin
		if(!arp_en)
		next=IDLE;
		else
		next=UNK;
	end
	default: next=UNK;
	endcase
end

always@(posedge clk or negedge rst)
begin
	if(!rst) current<=IDLE;
	else current<=next;
end

always@(posedge clk or negedge rst)
begin
	if(!rst) counter<=6'h00;
	else begin
		case(next)
		OP,
		ARP,
		R_ARP,
		UNK: counter<=counter+1;
		default:counter<=6'h00;
		endcase
	end
end

always@(posedge clk or negedge rst)
begin
	if(!rst) begin
		a_des_add<=48'h0000_0000_0000;
		a_des_ip<=32'h0000_0000;
		r_des_add<=48'h0000_0000_0000;
		r_des_ip<=32'h0000_0000;
		r_empty<=1'b1;		
	end	
	else begin
		if(next==ARP)begin
			case(counter)
			7,
			8,
			9,
			10,
			11,
			12,
			13:a_des_add<={a_des_add[39:0],arp_data};
			14,
			15,
			16,
			17:a_des_ip<={a_des_ip[23:0],arp_data};
			endcase
		end
		if(next==R_ARP) begin
			case(counter)
			7,
			8,
			9,
			10,
			11,
			12,
			13:r_des_add<={r_des_add[39:0],arp_data};
			14,
			15,
			16,
			17:r_des_ip<={r_des_ip[23:0],arp_data};
			endcase
		end
		if(next==LATCH) begin
			r_empty<=1'b0;
		end
		else if(r_rd) begin
			r_empty<=1'b1;
		end
	end
end
endmodule