content.xcp

具备GMII接口和ARP协议功能的千兆以太网控制器。经过Xilinx SPATAN-III FPGA验证, Verilog描述

# Xilinx CORE Generator 6.3i
SELECT Asynchronous_FIFO Spartan3 Xilinx,_Inc. 6.0
CSET read_error_sense = active_high
CSET read_count_width = 2
CSET write_acknowledge = false
CSET create_rpm = false
CSET read_acknowledge = false
CSET read_count = false
CSET write_error = false
CSET almost_full_flag = false
CSET almost_empty_flag = false
CSET memory_type = distributed
CSET read_error = false
CSET fifo_depth = 31
CSET component_name = content
CSET input_data_width = 16
CSET write_count = false
CSET write_acknowledge_sense = active_high
CSET read_acknowledge_sense = active_high
CSET write_error_sense = active_high
CSET write_count_width = 2
GENERATE