cache_control.v

来自「具备GMII接口和ARP协议功能的千兆以太网控制器。经过Xilinx SPATA」· Verilog 代码 · 共 138 行

module cache_control(
                     clk,
                     rst,
                     sending,
                     data_i,
                     desadd_i,                    
                     full_o,
                     /*******/
                     headadd_o,
                     length_o,
                     desadd_o,
                     latch_o,
                     full_i,
                     /*****/
                     addr_o,
                     data_o,
                     ram_en                     
                     );
       
       input clk;
       input rst;
       input sending;
       input[7:0] data_i;
       input[47:0] desadd_i; 
       output full_o;
       
       output headadd_o;
       reg headadd_o;
       output[15:0] length_o;
       output[47:0] desadd_o;
       reg[47:0] desadd_o;
       output latch_o;
       input full_i;
       
       output[10:0] addr_o;
       reg[10:0] addr_o;
       output[7:0] data_o;
       reg[7:0] data_o;
       output ram_en;
       reg ram_en;
       
       reg[4:0] current;
       reg[4:0] next;
       
       parameter IDLE=5'b00001, LOAD=5'b00010, SEND=5'b00100, 
                 LATCH=5'b01000, ERROR=5'b10000;

assign length_o=addr_o[9:0]+1;  //modified orignal is length_o=addr_o[10:0]+1
assign full_o=full_i;  
assign latch_o=current[3];     
always@(current or full_i or sending)
begin
	next=5'bxxxxx;
	case(current)
	IDLE: begin
		if(full_i&&sending)
		next=ERROR;
		else if(!full_i&&sending)
		next=LOAD;
		else
		next=IDLE;
	end
	LOAD: next=SEND;
	SEND: begin
		if(!sending)
		next=LATCH;
		else
		next=SEND;
	end
	LATCH: next=IDLE;
	ERROR: begin
		if(!sending)
		next=IDLE;
		else
		next=ERROR;
	end
	default: next=ERROR;
	endcase
end

always@(posedge clk or negedge rst)
begin
	if(!rst) current<=IDLE;
	else current<=next;
end

/*******************the ram operation*************/
always@(posedge clk or negedge rst)
begin
	if(!rst) begin
		ram_en<=1'b0;
		addr_o<=11'h000;
		data_o<=8'h00;
		headadd_o<=1'b0;
	end
	else begin
		case(next)
		IDLE: begin
			ram_en<=1'b0;
			if(current==LATCH)
			headadd_o<=headadd_o+1;
		end
		LOAD: begin
			addr_o<={headadd_o,10'h000};
			data_o<=data_i;
			ram_en<=1'b1;
			//headadd_o<=headadd_o+1;
		end
		SEND: begin
			data_o<=data_i;
			addr_o<=addr_o+1;
			ram_en<=1'b1;
		end
		LATCH: begin
			ram_en<=1'b0;
		//	headadd_o<=headadd_o+1;
		end
		default: begin
			addr_o<=11'h000;
			data_o<=8'h00;
			ram_en<=1'b0;
		end
	        endcase
	end
end
/************************the desadd********************/
always@(posedge clk or negedge rst)
begin
	if(!rst) begin
		desadd_o<=48'h0000_0000_0000;
	end
	else begin
		if(next==SEND&&current!=SEND)
		desadd_o<=desadd_i;
	end
end	     
endmodule