data_fifo.v

来自「具备GMII接口和ARP协议功能的千兆以太网控制器。经过Xilinx SPATA」· Verilog 代码 · 共 96 行

module data_fifo(
		clka,
		clkb,
		rst,
		datain,
		dataout,
		full,
		empty,
		rd,
		wr
		);
    input clka;
    input clkb;
    input rst;
    input[64:0] datain;
    output[64:0] dataout;
    reg[64:0] dataout;
    output full;
    reg full;
    output empty;
    reg empty;
    input rd;
    input wr;
    
    reg[1:0] wr_addr;
    reg[1:0] rd_addr;
    
    reg[1:0] wr_addr_60;
    reg[1:0] rd_addr_27;
    
    reg[64:0] mem[0:1];
    
always@(posedge clka or negedge rst)
begin
	if(!rst) wr_addr<=2'b00;
	else begin
		if(wr) begin
			wr_addr<=wr_addr+1;
			mem[wr_addr[0]]<=datain;
		end
	end
end
always@(posedge clkb or negedge rst)
begin
	if(!rst) begin
		 rd_addr<=2'b00;
		 dataout<=65'h0000_0000_0000_0000_0;
	end
	else begin
		if(rd) begin
			rd_addr<=rd_addr+1;
			dataout<=mem[rd_addr[0]];
		end
	end
end    
always@(posedge clkb or negedge rst)
begin
	if(!rst) begin
		empty<=1'b1;
	end
	else begin
		if(rd_addr!=wr_addr_60)
		empty<=1'b0;
		else
		empty<=1'b1;
	end
end
always@(posedge clka or negedge rst)
begin
	if(!rst) begin
		full<=1'b0;
	end
	else begin
		if(wr_addr[0]==rd_addr_27[0]&&wr_addr[1]!=rd_addr_27[1])
		full<=1'b1;
		else
		full<=1'b0;
	end
end
always@(posedge clkb or negedge rst)
begin
	if(!rst) wr_addr_60<=2'b00;
	else begin
		wr_addr_60<=wr_addr;
	end
end
always@(posedge clka or negedge rst)
begin
	if(!rst) rd_addr_27<=2'b00;
	else begin
		rd_addr_27<=rd_addr;
	end
end

endmodule