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具备GMII接口和ARP协议功能的千兆以太网控制器。经过Xilinx SPATAN-III FPGA验证, Verilog描述

# Xilinx CORE Generator 6.3i
# Username = winwalk
# COREGenPath = D:\Program Files\Xilinx\coregen
# ProjectPath = E:\Documentation\Digital\PROJECT\QAM\MAC\TEST_TRAN\ver1.4
# ExpandedProjectPath = E:\Documentation\Digital\PROJECT\QAM\MAC\TEST_TRAN\ver1.4
# OverwriteFiles = true
# Core name: content
# Number of Primitives in design: 211
# Number of CLBs used in design cannot be determined when there is no RPMed logic
# Number of Slices used in design cannot be determined when there is no RPMed logic
# Number of LUT sites used in design: 138
# Number of LUTs used in design: 74
# Number of REG used in design: 71
# Number of SRL16s used in design: 0
# Number of Distributed RAM primitives used in design: 32
# Number of Block Memories used in design: 0
# Number of Dedicated Multipliers used in design: 0
# Number of HU_SETs used: 0
# 
SET BusFormat = BusFormatAngleBracketNotRipped
SET XilinxFamily = Spartan3
SET OutputOption = OutputProducts
SET FlowVendor = Foundation_iSE
SET FormalVerification = None
SET OutputProducts = ImpNetlist ASYSymbol VHDLSim VerilogSim
SELECT Asynchronous_FIFO Spartan3 Xilinx,_Inc. 6.0
CSET read_error_sense = active_high
CSET read_count_width = 2
CSET write_acknowledge = false
CSET create_rpm = false
CSET read_acknowledge = false
CSET read_count = false
CSET write_error = false
CSET almost_full_flag = false
CSET almost_empty_flag = false
CSET memory_type = distributed
CSET read_error = false
CSET fifo_depth = 31
CSET component_name = content
CSET input_data_width = 16
CSET write_count = false
CSET write_acknowledge_sense = active_high
CSET read_acknowledge_sense = active_high
CSET write_error_sense = active_high
CSET write_count_width = 2
GENERATE