content.sym

具备GMII接口和ARP协议功能的千兆以太网控制器。经过Xilinx SPATAN-III FPGA验证, Verilog描述

VERSION 5
BEGIN SYMBOL content
SYMBOLTYPE BLOCK
TIMESTAMP 2007 7 15 9 55 50
SYMPIN 192 480 Input ainit
SYMPIN 0 48 Input din(15:0)
SYMPIN 0 144 Input wr_en
SYMPIN 0 176 Input wr_clk
SYMPIN 0 368 Input rd_en
SYMPIN 0 400 Input rd_clk
SYMPIN 384 48 Output full
SYMPIN 384 240 Output dout(15:0)
SYMPIN 384 272 Output empty
RECTANGLE N 32 0 352 448 
BEGIN DISPLAY 192 444 PIN ainit ATTR PinName
    ALIGNMENT BCENTER
    FONT 24 "Arial"
END DISPLAY
LINE N 192 448 192 480 
BEGIN DISPLAY 36 48 PIN din(15:0) ATTR PinName
    FONT 24 "Arial"
END DISPLAY
BEGIN LINE W 0 48 32 48 
END LINE
BEGIN DISPLAY 36 144 PIN wr_en ATTR PinName
    FONT 24 "Arial"
END DISPLAY
LINE N 0 144 32 144 
BEGIN DISPLAY 36 176 PIN wr_clk ATTR PinName
    FONT 24 "Arial"
END DISPLAY
LINE N 0 176 32 176 
BEGIN DISPLAY 36 368 PIN rd_en ATTR PinName
    FONT 24 "Arial"
END DISPLAY
LINE N 0 368 32 368 
BEGIN DISPLAY 36 400 PIN rd_clk ATTR PinName
    FONT 24 "Arial"
END DISPLAY
LINE N 0 400 32 400 
BEGIN DISPLAY 348 48 PIN full ATTR PinName
    ALIGNMENT RIGHT
    FONT 24 "Arial"
END DISPLAY
LINE N 352 48 384 48 
BEGIN DISPLAY 348 240 PIN dout(15:0) ATTR PinName
    ALIGNMENT RIGHT
    FONT 24 "Arial"
END DISPLAY
BEGIN LINE W 352 240 384 240 
END LINE
BEGIN DISPLAY 348 272 PIN empty ATTR PinName
    ALIGNMENT RIGHT
    FONT 24 "Arial"
END DISPLAY
LINE N 352 272 384 272 
END SYMBOL