fir321.tan.rpt

vhdl source,ver-fir-coefficient,simulink of fir with soft ware input

; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Do Min/Max analysis using Rise/Fall delays            ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Use Clock Latency for PLL offset                      ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                               ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; clk             ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; coef_in_clk     ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                                                                          ; To                                                                                                                                                   ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 317.76 MHz ( period = 3.147 ns )                    ; fir321_st:fir321_st_inst|ram_lut:Ur0_n_3_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_1jf1:auto_generated|ram_block1a10~portb_address_reg1               ; fir321_st:fir321_st_inst|ram_lut:Ur0_n_3_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_1jf1:auto_generated|q_b[1]                ; clk        ; clk      ; None                        ; None                      ; 2.509 ns                ;
; N/A                                     ; 317.76 MHz ( period = 3.147 ns )                    ; fir321_st:fir321_st_inst|ram_lut:Ur0_n_3_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_1jf1:auto_generated|ram_block1a10~portb_address_reg2               ; fir321_st:fir321_st_inst|ram_lut:Ur0_n_3_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_1jf1:auto_generated|q_b[1]                ; clk        ; clk      ; None                        ; None                      ; 2.509 ns                ;
; N/A                                     ; 317.76 MHz ( period = 3.147 ns )                    ; fir321_st:fir321_st_inst|ram_lut:Ur0_n_3_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_1jf1:auto_generated|ram_block1a10~portb_address_reg3               ; fir321_st:fir321_st_inst|ram_lut:Ur0_n_3_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_1jf1:auto_generated|q_b[1]                ; clk        ; clk      ; None                        ; None                      ; 2.509 ns                ;
; N/A                                     ; 317.76 MHz ( period = 3.147 ns )                    ; fir321_st:fir321_st_inst|ram_lut:Ur0_n_3_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_1jf1:auto_generated|ram_block1a10~portb_address_reg4               ; fir321_st:fir321_st_inst|ram_lut:Ur0_n_3_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_1jf1:auto_generated|q_b[1]                ; clk        ; clk      ; None                        ; None                      ; 2.509 ns                ;
; N/A                                     ; 317.76 MHz ( period = 3.147 ns )                    ; fir321_st:fir321_st_inst|ram_lut:Ur0_n_3_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_1jf1:auto_generated|ram_block1a10~portb_address_reg0               ; fir321_st:fir321_st_inst|ram_lut:Ur0_n_3_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_1jf1:auto_generated|q_b[0]                ; clk        ; clk      ; None                        ; None                      ; 2.509 ns                ;
; N/A                                     ; 317.76 MHz ( period = 3.147 ns )                    ; fir321_st:fir321_st_inst|ram_lut:Ur0_n_3_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_1jf1:auto_generated|ram_block1a10~portb_address_reg1               ; fir321_st:fir321_st_inst|ram_lut:Ur0_n_3_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_1jf1:auto_generated|q_b[0]                ; clk        ; clk      ; None                        ; None                      ; 2.509 ns                ;
; N/A                                     ; 317.76 MHz ( period = 3.147 ns )                    ; fir321_st:fir321_st_inst|ram_lut:Ur0_n_3_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_1jf1:auto_generated|ram_block1a10~portb_address_reg2               ; fir321_st:fir321_st_inst|ram_lut:Ur0_n_3_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_1jf1:auto_generated|q_b[0]                ; clk        ; clk      ; None                        ; None                      ; 2.509 ns                ;
; N/A                                     ; 317.76 MHz ( period = 3.147 ns )                    ; fir321_st:fir321_st_inst|ram_lut:Ur0_n_3_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_1jf1:auto_generated|ram_block1a10~portb_address_reg3               ; fir321_st:fir321_st_inst|ram_lut:Ur0_n_3_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_1jf1:auto_generated|q_b[0]                ; clk        ; clk      ; None                        ; None                      ; 2.509 ns                ;
; N/A                                     ; 317.76 MHz ( period = 3.147 ns )                    ; fir321_st:fir321_st_inst|ram_lut:Ur0_n_3_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_1jf1:auto_generated|ram_block1a10~portb_address_reg4               ; fir321_st:fir321_st_inst|ram_lut:Ur0_n_3_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_1jf1:auto_generated|q_b[0]                ; clk        ; clk      ; None                        ; None                      ; 2.509 ns                ;
; N/A                                     ; 317.76 MHz ( period = 3.147 ns )                    ; fir321_st:fir321_st_inst|ram_lut:Ur0_n_3_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_1jf1:auto_generated|ram_block1a10~portb_address_reg0               ; fir321_st:fir321_st_inst|ram_lut:Ur0_n_3_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_1jf1:auto_generated|q_b[10]               ; clk        ; clk      ; None                        ; None                      ; 2.509 ns                ;
; N/A                                     ; 317.76 MHz ( period = 3.147 ns )                    ; fir321_st:fir321_st_inst|ram_lut:Ur0_n_3_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_1jf1:auto_generated|ram_block1a10~portb_address_reg1               ; fir321_st:fir321_st_inst|ram_lut:Ur0_n_3_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_1jf1:auto_generated|q_b[10]               ; clk        ; clk      ; None                        ; None                      ; 2.509 ns                ;
; N/A                                     ; 317.76 MHz ( period = 3.147 ns )                    ; fir321_st:fir321_st_inst|ram_lut:Ur0_n_3_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_1jf1:auto_generated|ram_block1a10~portb_address_reg2               ; fir321_st:fir321_st_inst|ram_lut:Ur0_n_3_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_1jf1:auto_generated|q_b[10]               ; clk        ; clk      ; None                        ; None                      ; 2.509 ns                ;
; N/A                                     ; 317.76 MHz ( period = 3.147 ns )                    ; fir321_st:fir321_st_inst|ram_lut:Ur0_n_3_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_1jf1:auto_generated|ram_block1a10~portb_address_reg3               ; fir321_st:fir321_st_inst|ram_lut:Ur0_n_3_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_1jf1:auto_generated|q_b[10]               ; clk        ; clk      ; None                        ; None                      ; 2.509 ns                ;
; N/A                                     ; 317.76 MHz ( period = 3.147 ns )                    ; fir321_st:fir321_st_inst|ram_lut:Ur0_n_3_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_1jf1:auto_generated|ram_block1a10~portb_address_reg4               ; fir321_st:fir321_st_inst|ram_lut:Ur0_n_3_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_1jf1:auto_generated|q_b[10]               ; clk        ; clk      ; None                        ; None                      ; 2.509 ns                ;
; N/A                                     ; 317.76 MHz ( period = 3.147 ns )                    ; fir321_st:fir321_st_inst|ram_lut:Ur0_n_0_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_1jf1:auto_generated|ram_block1a10~portb_address_reg0               ; fir321_st:fir321_st_inst|ram_lut:Ur0_n_0_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_1jf1:auto_generated|q_b[9]                ; clk        ; clk      ; None                        ; None                      ; 2.509 ns                ;
; N/A                                     ; 317.76 MHz ( period = 3.147 ns )                    ; fir321_st:fir321_st_inst|ram_lut:Ur0_n_0_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_1jf1:auto_generated|ram_block1a10~portb_address_reg1               ; fir321_st:fir321_st_inst|ram_lut:Ur0_n_0_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_1jf1:auto_generated|q_b[9]                ; clk        ; clk      ; None                        ; None                      ; 2.509 ns                ;
; N/A                                     ; 317.76 MHz ( period = 3.147 ns )                    ; fir321_st:fir321_st_inst|ram_lut:Ur0_n_0_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_1jf1:auto_generated|ram_block1a10~portb_address_reg2               ; fir321_st:fir321_st_inst|ram_lut:Ur0_n_0_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_1jf1:auto_generated|q_b[9]                ; clk        ; clk      ; None                        ; None                      ; 2.509 ns                ;
; N/A                                     ; 317.76 MHz ( period = 3.147 ns )                    ; fir321_st:fir321_st_inst|ram_lut:Ur0_n_0_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_1jf1:auto_generated|ram_block1a10~portb_address_reg3               ; fir321_st:fir321_st_inst|ram_lut:Ur0_n_0_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_1jf1:auto_generated|q_b[9]                ; clk        ; clk      ; None                        ; None                      ; 2.509 ns                ;