fir321.tan.rpt

vhdl source,ver-fir-coefficient,simulink of fir with soft ware input

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+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                               ;
+------------------------------+-------+---------------+----------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------+-------------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                      ; From                                                                                                                                                            ; To                                                                                                                                                             ; From Clock  ; To Clock    ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------+-------------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 3.599 ns                         ; coef_in[8]                                                                                                                                                      ; fir321_st:fir321_st_inst|coef_in_conv:coef_conv|coef_in_inv[10]                                                                                                ;             ; coef_in_clk ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 7.159 ns                         ; fir321_st:fir321_st_inst|sadd_lpm_cen:Uadd_cen_l_0_n_0_n|pipe[0][8]                                                                                             ; fir_result[8]                                                                                                                                                  ; clk         ;             ; 0            ;
; Worst-case th                ; N/A   ; None          ; -0.060 ns                        ; rst                                                                                                                                                             ; fir321_st:fir321_st_inst|tdl_da_lc:Utdldalc0n|data_out[4]                                                                                                      ;             ; clk         ; 0            ;
; Clock Setup: 'clk'           ; N/A   ; None          ; 317.76 MHz ( period = 3.147 ns ) ; fir321_st:fir321_st_inst|ram_lut:Ur0_n_3_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_1jf1:auto_generated|ram_block1a10~portb_address_reg1 ; fir321_st:fir321_st_inst|ram_lut:Ur0_n_3_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_1jf1:auto_generated|q_b[1]                          ; clk         ; clk         ; 0            ;
; Clock Setup: 'coef_in_clk'   ; N/A   ; None          ; 319.18 MHz ( period = 3.133 ns ) ; fir321_st:fir321_st_inst|ram_lut:Ur0_n_8_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_d0g1:auto_generated|ram_block1a10~porta_datain_reg0  ; fir321_st:fir321_st_inst|ram_lut:Ur0_n_8_pp|ram_2pt_var_cen:ram|altsyncram:altsyncram_component|altsyncram_d0g1:auto_generated|ram_block1a10~porta_memory_reg0 ; coef_in_clk ; coef_in_clk ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;                                                                                                                                                                 ;                                                                                                                                                                ;             ;             ; 0            ;
+------------------------------+-------+---------------+----------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------+-------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1S10F484C5       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minumum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Clock Analysis Only                                   ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;