fir321_st_wr.v

vhdl source,ver-fir-coefficient,simulink of fir with soft ware input

// Generated by FIR Compiler
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2004 Altera Corporation
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// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera.  Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
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// any other related documentation or information provided by Altera or a
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// needed under any third party's intellectual property, are provided herein.
  
  
module fir321_st_wr(clk, rst, coef_we,coef_in,coef_in_clk,rdy_to_ld, done, data_in, fir_result);
parameter IN_WIDTH = 16;
parameter FACTOR = 4;
parameter OUT_WIDTH = 35;
parameter ACCUM_WIDTH = 35;
parameter COEF_WIDTH_IN= 18;
parameter COEF_SET_WIDTH = 2;
                                                                     
input  clk, rst;                                                     
input  [IN_WIDTH-1:0] data_in;                                     
input  coef_we;
input  coef_in_clk;
input  [COEF_WIDTH_IN-1:0] coef_in;
output rdy_to_ld, done;                                           
output [OUT_WIDTH- 1:0] fir_result;                               
                                                                     
wire rdy_to_ld;                                                      
wire rdy_to_ld_int;                                                      
wire done;                                                           
wire rdy_out;                                                        
                                                                     
wire [OUT_WIDTH- 1:0] fir_result;                               
wire [OUT_WIDTH - 1:0] fir_int_res;                               
wire [COEF_SET_WIDTH - 1 :0] coef_set_cnt;                            
wire [COEF_WIDTH_IN-1:0] coef_in_reg;				
wire [1:0] coef_set_in_cnt_set;		
wire [1:0] coef_set_in_cnt;		
wire coef_we_reg;                                    
                                                                     
                                                                     
fir321_st u0(.clk(clk),                                        
	    .rst(rst),                                                      
	    .data_in(data_in),                                              
	    .coef_in(coef_in),                                        
	    .coef_we(coef_we),                                        
	    .coef_in_clk(coef_in_clk),                                
	    .coef_set_in(coef_set_in_cnt_set),                                
	    .coef_set(coef_set_cnt),                                        
	    .done(done),                                                    
	    .rdy_to_ld(rdy_to_ld_int),                                          
	    .fir_result(fir_int_res)                                         
	    );                                                              
                                                                     
assign fir_result = fir_int_res;                            

mr_upc_wr u1(.clk(clk),                                            
		        .rst(rst),                                                      
		        .cen(rdy_to_ld_int),                                                
		        .cnt_out(coef_set_cnt)                                          
		       );                                                              
defparam u1.SIZE = FACTOR;                                      
defparam u1.OUT_WIDTH = COEF_SET_WIDTH;                             
                                                                     
mr_lrdy_wr u2(.clk(clk),										
				 .rst(rst),                       
				 .clk_en(1'b1),   
				 .rdy_to_ld_int(rdy_to_ld_int),              
				 .rdy_out(rdy_to_ld)              
				);            
					                                  
defparam u2.SIZE = 16;                 
defparam u2.OUT_WIDTH = 4;    
defparam u2.CNT_VAL = 4;
                                                                     
//Multi-Rate Coeficient Reload Logic
assign coef_set_in_cnt_set  = coef_set_in_cnt;														
mr_upc_reload_wr ure1(.clk(coef_in_clk),								
		          .rst(rst),								
		          .cen(coef_we),							
		          .cnt_out(coef_set_in_cnt)				
		       );										
defparam ure1.SIZE = 16;					
defparam ure1.CNT_WIDTH = 4;					
defparam ure1.OUT_WIDTH = 2;				
														
														
endmodule													
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