fir321.map.rpt

vhdl source,ver-fir-coefficient,simulink of fir with soft ware input

; Auto Carry Chains                                                  ; On           ; On            ;
; Auto Open-Drain Pins                                               ; On           ; On            ;
; Remove Duplicate Logic                                             ; On           ; On            ;
; Perform WYSIWYG Primitive Resynthesis                              ; Off          ; Off           ;
; Perform gate-level register retiming                               ; Off          ; Off           ;
; Allow register retiming to trade off Tsu/Tco with Fmax             ; On           ; On            ;
; Auto ROM Replacement                                               ; On           ; On            ;
; Auto RAM Replacement                                               ; On           ; On            ;
; Auto DSP Block Replacement                                         ; On           ; On            ;
; Auto Shift Register Replacement                                    ; On           ; On            ;
; Auto Clock Enable Replacement                                      ; On           ; On            ;
; Allows Synchronous Control Signal Usage in Normal Mode Logic Cells ; On           ; On            ;
; Auto RAM Block Balancing                                           ; On           ; On            ;
; Auto Resource Sharing                                              ; Off          ; Off           ;
; Allow Any RAM Size For Recognition                                 ; Off          ; Off           ;
; Allow Any ROM Size For Recognition                                 ; Off          ; Off           ;
; Allow Any Shift Register Size For Recognition                      ; Off          ; Off           ;
; Enable M512 Memory Blocks                                          ; On           ; On            ;
+--------------------------------------------------------------------+--------------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                                  ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                                        ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------+
; 3:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; Yes        ; |fir321|fir321_st:fir321_st_inst|addr_cnt_up:addr_cnt|cnt_out[0]  ;
; 3:1                ; 80 bits   ; 160 LEs       ; 80 LEs               ; 80 LEs                 ; Yes        ; |fir321|fir321_st:fir321_st_inst|tdl_da_lc:Utdldalc6n|data_out[5] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------+


+----------------------------------------------------------------+
; WYSIWYG Cells                                                  ;
+--------------------------------------------------------+-------+
; Statistic                                              ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells                                ; 171   ;
; Number of synthesis-generated cells                    ; 149   ;
; Number of WYSIWYG LUTs                                 ; 171   ;
; Number of synthesis-generated LUTs                     ; 92    ;
; Number of WYSIWYG registers                            ; 170   ;
; Number of synthesis-generated registers                ; 140   ;
; Number of cells with combinational logic only          ; 10    ;
; Number of cells with registers only                    ; 57    ;
; Number of cells with combinational logic and registers ; 253   ;
+--------------------------------------------------------+-------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 310   ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 7     ;
; Number of registers using Asynchronous Clear ; 8     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 85    ;
; Number of registers using Output Enable      ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-----------+
; Hierarchy ;
+-----------+
fir321
 |-- fir321_st:fir321_st_inst
      |-- sadd:U_0_sym_add
      |-- sadd:U_1_sym_add
      |-- sadd:U_2_sym_add
      |-- sadd:U_3_sym_add
      |-- sadd:U_4_sym_add
      |-- sadd_lpm_cen:Uadd_0_lut_l_0_n_0_n
      |-- sadd_lpm_cen:Uadd_0_lut_l_0_n_1_n
      |-- sadd_lpm_cen:Uadd_0_lut_l_0_n_2_n
      |-- sadd_lpm_cen:Uadd_0_lut_l_0_n_3_n
      |-- sadd_lpm_cen:Uadd_0_lut_l_0_n_4_n
           |-- altshift_taps:pipe_rtl_1
                |-- shift_taps_3lg:auto_generated
                     |-- add_sub_rod:add_sub2
                     |-- altsyncram_b5q:altsyncram4
                     |-- cntr_2gc:cntr1
      |-- sadd_lpm_cen:Uadd_0_lut_l_1_n_0_n
      |-- sadd_lpm_cen:Uadd_0_lut_l_1_n_1_n
      |-- sadd_lpm_cen:Uadd_0_lut_l_1_n_2_n
      |-- sadd_lpm_cen:Uadd_0_lut_l_2_n_0_n
      |-- sadd_lpm_cen:Uadd_0_lut_l_2_n_1_n
      |-- sadd_lpm_cen:Uadd_0_lut_l_3_n_0_n
      |-- sadd_lpm_cen:Uadd_cen_l_0_n_0_n
      |-- par_ctrl:Uctrl
           |-- lpm_counter:cnt_rtl_0
                |-- cntr_sv7:auto_generated
      |-- mac_tl:Umtl
      |-- ram_lut:Ur0_n_0_pp
           |-- ram_2pt_var_cen:ram
                |-- altsyncram:altsyncram_component