rate_adjust.hier_info

VerilogHDL开发

|Rate_Adjust
En => always0~0.IN0
Reset => always0~0.IN1
Rate_Adjust_Select => always0~1.IN0
Rate_Data[0] => always0~3.IN0
Rate_Data[1] => always0~4.IN0
Rate_Data[2] => always0~5.IN0
Rate_Data[3] => always0~6.IN0
Rate_Data[4] => always0~7.IN0
Rate_Data[5] => always0~8.IN0
Rate_Data[6] => always0~9.IN0
Rate_Data[7] => always0~10.IN0
Rate_Data[8] => always0~11.IN0
Rate_Data[9] => always0~12.IN0
Rate_Data[10] => always0~13.IN0
Rate_Data[11] => always0~14.IN0
Rate_Data[12] => always0~15.IN0
Rate_Data[13] => always0~16.IN0
Rate_Data[14] => always0~17.IN0
Rate_Data[15] => always0~18.IN0
Rate_Set[0] => always0~3.IN1
Rate_Set[1] => always0~4.IN1
Rate_Set[2] => always0~5.IN1
Rate_Set[3] => always0~6.IN1
Rate_Set[4] => always0~7.IN1
Rate_Set[5] => always0~8.IN1
Rate_Set[6] => always0~9.IN1
Rate_Set[7] => always0~10.IN1
Rate_Set[8] => always0~11.IN1
Rate_Set[9] => always0~12.IN1
Rate_Set[10] => always0~13.IN1
Rate_Set[11] => always0~14.IN1
Rate_Set[12] => always0~15.IN1
Rate_Set[13] => always0~16.IN1
Rate_Set[14] => always0~17.IN1
Rate_Set[15] => always0~18.IN1
Rate_Adjust_Out <= Rate_Adjust_Out~0.DB_MAX_OUTPUT_PORT_TYPE