rate_adjust.map.summary

来自「VerilogHDL开发」· SUMMARY 代码 · 共 9 行

Flow Status : Successful - Fri Aug 04 17:16:59 2006
Quartus II Version : 4.2 Build 157 12/07/2004 SJ Full Version
Revision Name : Rate_Adjust
Top-level Entity Name : Rate_Adjust
Family : MAX7000S
Met timing requirements : N/A
Total macrocells : 9
Total pins : 36